Re: GAL ... la la la ...
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From: jfox_at_nospam_friko6.onet.pl (J.F.)
Subject: Re: GAL ... la la la ...
Date: Sun, 01 Aug 1999 20:58:08 GMT
On Sat, 31 Jul 1999 18:12:34 GMT, Juliusz wrote:
To trywialna sprawa programowac GALA w VHDL
no macie przyklad - 10 bitowy licznik, z zerowaniem-resetem i kierunkiem
liczenia i enable.
40 linijek programu i to ma byc trywialnie ?
Toz to rownania mniej zajmuja, a co dopiero makro :-)
Zajmujie ledwo ponad polowe 22V10. Zmiesci sie jeszcze
kupa innego dobra.
68% to ponad 2/3 a nie ledwo ponad polowe :-)
zuzywasz tez 10 makrocel z 10, i 13 PT z 16 dostepnych.
Duzo wiecej sie nie zmiesci - zadnego wyjcia wolnego nie masz,
mozesz myslec o dodatkowych funkcjach licznika.
Np. wpis rownolegly. Watpie by zmiescilo sie np liczenie
w BCD a nie tylko binarnie.
A swoja droga ... mozesz podeslac wygenerowane funkcje
dla makrocel? Bo jak na moj gust, to najstarszy bit licznika
wymaga 10PT dla kazdego kierunku zliczania. Dwa kierunki - 20PT.
a max w 22V10 to 16 :-)
J.
From: "Juliusz" <juliusz_at_nospam_multi-ip.com.pl>
Subject: Re: GAL ... la la la ...
Date: Sun, 01 Aug 1999 21:17:48 GMT
A swoja droga ... mozesz podeslac wygenerowane funkcje
dla makrocel? Bo jak na moj gust, to najstarszy bit licznika
wymaga 10PT dla kazdego kierunku zliczania. Dwa kierunki - 20PT.
a max w 22V10 to 16 :-)
| | | | | | |
_______________
-| |-
-| |-
-| |-
-| CYPRESS |-
-| |-
-| |- Warp VHDL Synthesis Compiler: Version 4 IR x90
-| |- Copyright (C) 1991, 1992, 1993,
| _____________| 1994, 1995, 1996, 1997 Cypress Semiconductor
| | | | | | |
======================================================================
Compiling: gal0.vhd
Options: -q -yv2 -yu -e10 -w100 -o2 -ygs -fO -fP -v10 -dc22v10 -pPALCE22V
10-7PC gal0.vhd
======================================================================
C:\warp\bin\vhdlfe.exe V4 IR x90: VHDL parser
Sat Jul 31 17:37:27 1999
Library 'work' => directory 'lc22v10'
Linking 'C:\warp\lib\common\work\cypress.vif'.
Library 'ieee' => directory 'C:\warp\lib\ieee\work'
Linking 'C:\warp\lib\ieee\work\stdlogic.vif'.
Library 'work' => directory 'lc22v10'
Linking 'C:\warp\lib\common\stdlogic\lpmpkg.vif'.
Linking 'C:\warp\lib\common\stdlogic\rtlpkg.vif'.
Linking 'C:\warp\lib\common\stdlogic\mod_cnst.vif'.
Linking 'C:\warp\lib\common\stdlogic\mod_mth.vif'.
Linking 'C:\warp\lib\common\stdlogic\mod_gen.vif'.
gal0.vhd (line 28, col 26): Note: Substituting module 'add_vi_ss' for '+'.
gal0.vhd (line 30, col 26): Note: Substituting module 'sub_vi_ss' for '-'.
C:\warp\bin\vhdlfe.exe: No errors.
C:\warp\bin\tovif.exe V4 IR x90: High-level synthesis
Sat Jul 31 17:37:29 1999
Linking 'C:\warp\lib\common\work\cypress.vif'.
Linking 'C:\warp\lib\ieee\work\stdlogic.vif'.
Linking 'C:\warp\lib\common\stdlogic\lpmpkg.vif'.
Linking 'C:\warp\lib\common\stdlogic\rtlpkg.vif'.
Linking 'C:\warp\lib\common\stdlogic\mod_cnst.vif'.
Linking 'C:\warp\lib\common\stdlogic\mod_mth.vif'.
Linking 'C:\warp\lib\common\stdlogic\mod_gen.vif'.
Note: Removing wires from arch. 'generic_instance' of entity
'fdec_generic2'.
Removing left side of wire: b(0) <= bin.
Note: Removing wires from arch. 'generic_instance' of entity
'sub_ss_generic1'.
Removing left side of wire: a(9) <= aa(9).
Removing left side of wire: a(8) <= aa(8).
Removing left side of wire: a(7) <= aa(7).
Removing left side of wire: a(6) <= aa(6).
Removing left side of wire: a(5) <= aa(5).
Removing left side of wire: a(4) <= aa(4).
Removing left side of wire: a(3) <= aa(3).
Removing left side of wire: a(2) <= aa(2).
Removing left side of wire: a(1) <= aa(1).
Removing left side of wire: a(0) <= aa(0).
Removing left side of wire: b(9) <= bb(9).
Removing left side of wire: b(8) <= bb(8).
Removing left side of wire: b(7) <= bb(7).
Removing left side of wire: b(6) <= bb(6).
Removing left side of wire: b(5) <= bb(5).
Removing left side of wire: b(4) <= bb(4).
Removing left side of wire: b(3) <= bb(3).
Removing left side of wire: b(2) <= bb(2).
Removing left side of wire: b(1) <= bb(1).
Removing left side of wire: b(0) <= bb(0).
Note: Removing wires from arch. 'generic_instance' of entity
'sub_vi_ss_generic0'.
Removing left side of wire: b(9) <= '0'.
Removing left side of wire: b(8) <= '0'.
Removing left side of wire: b(7) <= '0'.
Removing left side of wire: b(6) <= '0'.
Removing left side of wire: b(5) <= '0'.
Removing left side of wire: b(4) <= '0'.
Removing left side of wire: b(3) <= '0'.
Removing left side of wire: b(2) <= '0'.
Removing left side of wire: b(1) <= '0'.
Removing left side of wire: b(0) <= '1'.
Note: Removing wires from arch. 'generic_instance' of entity
'finc_generic5'.
Removing left side of wire: b(0) <= cin.
Note: Removing wires from arch. 'generic_instance' of entity
'add_ss_generic4'.
Removing left side of wire: a(9) <= aa(9).
Removing left side of wire: a(8) <= aa(8).
Removing left side of wire: a(7) <= aa(7).
Removing left side of wire: a(6) <= aa(6).
Removing left side of wire: a(5) <= aa(5).
Removing left side of wire: a(4) <= aa(4).
Removing left side of wire: a(3) <= aa(3).
Removing left side of wire: a(2) <= aa(2).
Removing left side of wire: a(1) <= aa(1).
Removing left side of wire: a(0) <= aa(0).
Removing left side of wire: b(9) <= bb(9).
Removing left side of wire: b(8) <= bb(8).
Removing left side of wire: b(7) <= bb(7).
Removing left side of wire: b(6) <= bb(6).
Removing left side of wire: b(5) <= bb(5).
Removing left side of wire: b(4) <= bb(4).
Removing left side of wire: b(3) <= bb(3).
Removing left side of wire: b(2) <= bb(2).
Removing left side of wire: b(1) <= bb(1).
Removing left side of wire: b(0) <= bb(0).
Note: Removing wires from arch. 'generic_instance' of entity
'add_vi_ss_generic3'.
Removing left side of wire: b(9) <= '0'.
Removing left side of wire: b(8) <= '0'.
Removing left side of wire: b(7) <= '0'.
Removing left side of wire: b(6) <= '0'.
Removing left side of wire: b(5) <= '0'.
Removing left side of wire: b(4) <= '0'.
Removing left side of wire: b(3) <= '0'.
Removing left side of wire: b(2) <= '0'.
Removing left side of wire: b(1) <= '0'.
Removing left side of wire: b(0) <= '1'.
Note: Removing wires from arch. 'arch_counter' of entity 'counter'.
C:\warp\bin\tovif.exe: No errors.
C:\warp\bin\topld.exe V4 IR x96: Synthesis and optimization
Sat Jul 31 17:37:32 1999
Linking 'C:\warp\lib\common\work\cypress.vif'.
Linking 'C:\warp\lib\ieee\work\stdlogic.vif'.
Linking 'C:\warp\lib\common\stdlogic\lpmpkg.vif'.
Linking 'C:\warp\lib\common\stdlogic\rtlpkg.vif'.
Linking 'C:\warp\lib\common\stdlogic\mod_cnst.vif'.
Linking 'C:\warp\lib\common\stdlogic\mod_mth.vif'.
Linking 'C:\warp\lib\common\stdlogic\mod_gen.vif'.
Linking 'C:\warp\lib\lc22v10\stdlogic\c22v10.vif'.
----------------------------------------------------------
Detecting unused logic.
----------------------------------------------------------
------------------------------------------------------
Alias Detection
------------------------------------------------------
Aliasing ile_8R to ile_9R
Aliasing ile_8S to ile_9S
Aliasing ile_7R to ile_9R
Aliasing ile_7S to ile_9S
Aliasing ile_6R to ile_9R
Aliasing ile_6S to ile_9S
Aliasing ile_5R to ile_9R
Aliasing ile_5S to ile_9S
Aliasing ile_4R to ile_9R
Aliasing ile_4S to ile_9S
Aliasing ile_3R to ile_9R
Aliasing ile_3S to ile_9S
Aliasing ile_2R to ile_9R
Aliasing ile_2S to ile_9S
Aliasing ile_1R to ile_9R
Aliasing ile_1S to ile_9S
Aliasing ile_0R to ile_9R
Aliasing ile_0S to ile_9S
Aliasing MODIN1_8 to count(8)
Aliasing MODIN1_9 to count(9)
Aliasing MODIN1_7 to count(7)
Aliasing MODIN1_6 to count(6)
Aliasing MODIN1_5 to count(5)
Aliasing MODIN1_4 to count(4)
Aliasing MODIN1_3 to count(3)
Aliasing MODIN1_2 to count(2)
Aliasing MODIN1_1 to count(1)
Aliasing MODIN1_0 to count(0)
Aliasing MODIN2_8 to count(8)
Aliasing MODIN2_9 to count(9)
Aliasing MODIN2_7 to count(7)
Aliasing MODIN2_6 to count(6)
Aliasing MODIN2_5 to count(5)
Aliasing MODIN2_4 to count(4)
Aliasing MODIN2_3 to count(3)
Aliasing MODIN2_2 to count(2)
Aliasing MODIN2_1 to count(1)
Aliasing MODIN2_0 to count(0)
Aliasing MODULE_2_g2_a0_g1_z1_s0_g1_u0 c0 to
MODULE_1_g2_a0_g1_z1_s0_g1_u0 c0
Removing Rhs of wire count(9)[4] = ile_9[14]
Removing Rhs of wire count(8)[5] = ile_8[17]
Removing Rhs of wire count(7)[6] = ile_7[20]
Removing Rhs of wire count(6)[7] = ile_6[23]
Removing Rhs of wire count(5)[8] = ile_5[26]
Removing Rhs of wire count(4)[9] = ile_4[29]
Removing Rhs of wire count(3)[10] = ile_3[32]
Removing Rhs of wire count(2)[11] = ile_2[35]
Removing Rhs of wire count(1)[12] = ile_1[38]
Removing Rhs of wire count(0)[13] = ile_0[41]
Removing Rhs of wire add_vi_ss_MODGEN_1_9[15] = MODULE_2_g2_a0 s9[94]
Removing Rhs of wire sub_vi_ss_MODGEN_2_9[16] = MODULE_1_g2_a0 d9[64]
Removing Rhs of wire add_vi_ss_MODGEN_1_8[18] = MODULE_2_g2_a0 s8[95]
Removing Rhs of wire sub_vi_ss_MODGEN_2_8[19] = MODULE_1_g2_a0 d8[65]
Removing Rhs of wire add_vi_ss_MODGEN_1_7[21] = MODULE_2_g2_a0 s7[96]
Removing Rhs of wire sub_vi_ss_MODGEN_2_7[22] = MODULE_1_g2_a0 d7[66]
Removing Rhs of wire add_vi_ss_MODGEN_1_6[24] = MODULE_2_g2_a0 s6[97]
Removing Rhs of wire sub_vi_ss_MODGEN_2_6[25] = MODULE_1_g2_a0 d6[67]
Removing Rhs of wire add_vi_ss_MODGEN_1_5[27] = MODULE_2_g2_a0 s5[98]
Removing Rhs of wire sub_vi_ss_MODGEN_2_5[28] = MODULE_1_g2_a0 d5[68]
Removing Rhs of wire add_vi_ss_MODGEN_1_4[30] = MODULE_2_g2_a0 s4[99]
Removing Rhs of wire sub_vi_ss_MODGEN_2_4[31] = MODULE_1_g2_a0 d4[69]
Removing Rhs of wire add_vi_ss_MODGEN_1_3[33] = MODULE_2_g2_a0 s3[100]
Removing Rhs of wire sub_vi_ss_MODGEN_2_3[34] = MODULE_1_g2_a0 d3[70]
Removing Rhs of wire add_vi_ss_MODGEN_1_2[36] = MODULE_2_g2_a0 s2[101]
Removing Rhs of wire sub_vi_ss_MODGEN_2_2[37] = MODULE_1_g2_a0 d2[71]
Removing Rhs of wire add_vi_ss_MODGEN_1_1[39] = MODULE_2_g2_a0 s1[102]
Removing Rhs of wire sub_vi_ss_MODGEN_2_1[40] = MODULE_1_g2_a0 d1[72]
Removing Rhs of wire add_vi_ss_MODGEN_1_0[42] = MODULE_2_g2_a0 s0[103]
Removing Rhs of wire sub_vi_ss_MODGEN_2_0[43] = MODULE_1_g2_a0 d0[73]
Removing Lhs of wire ile_8R[46] = ile_9R[44]
Removing Lhs of wire ile_8S[47] = ile_9S[45]
Removing Lhs of wire ile_7R[48] = ile_9R[44]
Removing Lhs of wire ile_7S[49] = ile_9S[45]
Removing Lhs of wire ile_6R[50] = ile_9R[44]
Removing Lhs of wire ile_6S[51] = ile_9S[45]
Removing Lhs of wire ile_5R[52] = ile_9R[44]
Removing Lhs of wire ile_5S[53] = ile_9S[45]
Removing Lhs of wire ile_4R[54] = ile_9R[44]
Removing Lhs of wire ile_4S[55] = ile_9S[45]
Removing Lhs of wire ile_3R[56] = ile_9R[44]
Removing Lhs of wire ile_3S[57] = ile_9S[45]
Removing Lhs of wire ile_2R[58] = ile_9R[44]
Removing Lhs of wire ile_2S[59] = ile_9S[45]
Removing Lhs of wire ile_1R[60] = ile_9R[44]
Removing Lhs of wire ile_1S[61] = ile_9S[45]
Removing Lhs of wire ile_0R[62] = ile_9R[44]
Removing Lhs of wire ile_0S[63] = ile_9S[45]
Removing Lhs of wire MODIN1_8[75] = count(8)[5]
Removing Lhs of wire MODIN1_9[77] = count(9)[4]
Removing Lhs of wire MODIN1_7[78] = count(7)[6]
Removing Lhs of wire MODIN1_6[80] = count(6)[7]
Removing Lhs of wire MODIN1_5[82] = count(5)[8]
Removing Lhs of wire MODIN1_4[84] = count(4)[9]
Removing Lhs of wire MODIN1_3[86] = count(3)[10]
Removing Lhs of wire MODIN1_2[88] = count(2)[11]
Removing Lhs of wire MODIN1_1[90] = count(1)[12]
Removing Lhs of wire MODIN1_0[92] = count(0)[13]
Removing Lhs of wire MODIN2_8[105] = count(8)[5]
Removing Lhs of wire MODIN2_9[107] = count(9)[4]
Removing Lhs of wire MODIN2_7[108] = count(7)[6]
Removing Lhs of wire MODIN2_6[110] = count(6)[7]
Removing Lhs of wire MODIN2_5[112] = count(5)[8]
Removing Lhs of wire MODIN2_4[114] = count(4)[9]
Removing Lhs of wire MODIN2_3[116] = count(3)[10]
Removing Lhs of wire MODIN2_2[118] = count(2)[11]
Removing Lhs of wire MODIN2_1[120] = count(1)[12]
Removing Lhs of wire MODIN2_0[122] = count(0)[13]
Removing Lhs of wire MODULE_2_g2_a0_g1_z1_s0_g1_u0 c0[123] =
MODULE_1_g2_a0_g1_z1_s0_g1_u0 c0[93]
------------------------------------------------------
Aliased 0 equations, 69 wires.
------------------------------------------------------
----------------------------------------------------------
Circuit simplification
----------------------------------------------------------
Substituting virtuals - pass 1:
Note: Virtual equation for 'MODULE_1_g2_a0_g1_z1_s0_g1_u0 c0' has been
expanded (cost = 0):
MODULE_1_g2_a0_g1_z1_s0_g1_u0 c0 <= ('1') ;
Note: Virtual equation for 'sub_vi_ss_MODGEN_2_0' has been expanded (cost =
0):
sub_vi_ss_MODGEN_2_0 <= (not count(0));
Substituting virtuals - pass 2:
Note: Virtual equation for 'MODULE_2_g2_a0_g1_z1_s0_g1_u0 c1' has been
expanded (cost = 0):
MODULE_2_g2_a0_g1_z1_s0_g1_u0 c1 <= (count(0));
Note: Virtual equation for 'MODULE_1_g2_a0_g1_z1_s0_g1_u0 c1' has been
expanded (cost = 0):
MODULE_1_g2_a0_g1_z1_s0_g1_u0 c1 <= (not count(0));
Note: Virtual equation for 'add_vi_ss_MODGEN_1_0' has been expanded (cost =
0):
add_vi_ss_MODGEN_1_0 <= (not count(0));
Substituting virtuals - pass 3:
Note: Virtual equation for 'MODULE_2_g2_a0_g1_z1_s0_g1_u0 c2' has been
expanded (cost = 3):
MODULE_2_g2_a0_g1_z1_s0_g1_u0 c2 <= ((count(1) and count(0)));
Note: Virtual equation for 'MODULE_1_g2_a0_g1_z1_s0_g1_u0 c2' has been
expanded (cost = 3):
MODULE_1_g2_a0_g1_z1_s0_g1_u0 c2 <= ((not count(1) and not count(0)));
Note: Virtual equation for 'add_vi_ss_MODGEN_1_1' has been expanded (cost =
2):
add_vi_ss_MODGEN_1_1 <= ((not count(0) and count(1))
OR (not count(1) and count(0)));
Note: Virtual equation for 'sub_vi_ss_MODGEN_2_1' has been expanded (cost =
2):
sub_vi_ss_MODGEN_2_1 <= ((count(1) and count(0))
OR (not count(1) and not count(0)));
Substituting virtuals - pass 4:
Note: Virtual equation for 'MODULE_2_g2_a0_g1_z1_s0_g1_u0 c3' has been
expanded (cost = 3):
MODULE_2_g2_a0_g1_z1_s0_g1_u0 c3 <= ((count(2) and count(1) and count(0)));
Note: Virtual equation for 'MODULE_1_g2_a0_g1_z1_s0_g1_u0 c3' has been
expanded (cost = 3):
MODULE_1_g2_a0_g1_z1_s0_g1_u0 c3 <= ((not count(2) and not count(1) and not
count(0)));
Note: Virtual equation for 'add_vi_ss_MODGEN_1_2' has been expanded (cost =
3):
add_vi_ss_MODGEN_1_2 <= ((not count(1) and count(2))
OR (not count(0) and count(2))
OR (not count(2) and count(1) and count(0)));
Note: Virtual equation for 'sub_vi_ss_MODGEN_2_2' has been expanded (cost =
3):
sub_vi_ss_MODGEN_2_2 <= ((count(2) and count(1))
OR (count(2) and count(0))
OR (not count(2) and not count(1) and not count(0)));
Substituting virtuals - pass 5:
Note: Virtual equation for 'MODULE_2_g2_a0_g1_z1_s0_g1_u0 c4' has been
expanded (cost = 3):
MODULE_2_g2_a0_g1_z1_s0_g1_u0 c4 <= ((count(3) and count(2) and count(1)
and count(0)));
Note: Virtual equation for 'MODULE_1_g2_a0_g1_z1_s0_g1_u0 c4' has been
expanded (cost = 3):
MODULE_1_g2_a0_g1_z1_s0_g1_u0 c4 <= ((not count(3) and not count(2) and not
count(1) and not count(0)));
Note: Virtual equation for 'add_vi_ss_MODGEN_1_3' has been expanded (cost =
4):
add_vi_ss_MODGEN_1_3 <= ((not count(2) and count(3))
OR (not count(1) and count(3))
OR (not count(0) and count(3))
OR (not count(3) and count(2) and count(1) and count(0)));
Note: Virtual equation for 'sub_vi_ss_MODGEN_2_3' has been expanded (cost =
4):
sub_vi_ss_MODGEN_2_3 <= ((count(3) and count(2))
OR (count(3) and count(1))
OR (count(3) and count(0))
OR (not count(3) and not count(2) and not count(1) and not count(0)));
Substituting virtuals - pass 6:
Note: Virtual equation for 'MODULE_2_g2_a0_g1_z1_s0_g1_u0 c5' has been
expanded (cost = 3):
MODULE_2_g2_a0_g1_z1_s0_g1_u0 c5 <= ((count(4) and count(3) and count(2)
and count(1) and count(0)));
Note: Virtual equation for 'MODULE_1_g2_a0_g1_z1_s0_g1_u0 c5' has been
expanded (cost = 3):
MODULE_1_g2_a0_g1_z1_s0_g1_u0 c5 <= ((not count(4) and not count(3) and not
count(2) and not count(1) and not count(0)));
Note: Virtual equation for 'add_vi_ss_MODGEN_1_4' has been expanded (cost =
5):
add_vi_ss_MODGEN_1_4 <= ((not count(3) and count(4))
OR (not count(2) and count(4))
OR (not count(1) and count(4))
OR (not count(0) and count(4))
OR (not count(4) and count(3) and count(2) and count(1) and count(0)));
Note: Virtual equation for 'sub_vi_ss_MODGEN_2_4' has been expanded (cost =
5):
sub_vi_ss_MODGEN_2_4 <= ((count(4) and count(3))
OR (count(4) and count(2))
OR (count(4) and count(1))
OR (count(4) and count(0))
OR (not count(4) and not count(3) and not count(2) and not count(1) and not
count(0)));
Substituting virtuals - pass 7:
Note: Virtual equation for 'MODULE_2_g2_a0_g1_z1_s0_g1_u0 c6' has been
expanded (cost = 3):
MODULE_2_g2_a0_g1_z1_s0_g1_u0 c6 <= ((count(5) and count(4) and count(3)
and count(2) and count(1) and count(0)));
Note: Virtual equation for 'MODULE_1_g2_a0_g1_z1_s0_g1_u0 c6' has been
expanded (cost = 3):
MODULE_1_g2_a0_g1_z1_s0_g1_u0 c6 <= ((not count(5) and not count(4) and not
count(3) and not count(2) and not count(1) and not count(0)));
Note: Virtual equation for 'add_vi_ss_MODGEN_1_5' has been expanded (cost =
6):
add_vi_ss_MODGEN_1_5 <= ((not count(4) and count(5))
OR (not count(3) and count(5))
OR (not count(2) and count(5))
OR (not count(1) and count(5))
OR (not count(0) and count(5))
OR (not count(5) and count(4) and count(3) and count(2) and count(1) and
count(0)));
Note: Virtual equation for 'sub_vi_ss_MODGEN_2_5' has been expanded (cost =
6):
sub_vi_ss_MODGEN_2_5 <= ((count(5) and count(4))
OR (count(5) and count(3))
OR (count(5) and count(2))
OR (count(5) and count(1))
OR (count(5) and count(0))
OR (not count(5) and not count(4) and not count(3) and not count(2) and not
count(1) and not count(0)));
Substituting virtuals - pass 8:
Note: Virtual equation for 'MODULE_2_g2_a0_g1_z1_s0_g1_u0 c7' has been
expanded (cost = 3):
MODULE_2_g2_a0_g1_z1_s0_g1_u0 c7 <= ((count(6) and count(5) and count(4)
and count(3) and count(2) and count(1) and count(0)));
Note: Virtual equation for 'MODULE_1_g2_a0_g1_z1_s0_g1_u0 c7' has been
expanded (cost = 3):
MODULE_1_g2_a0_g1_z1_s0_g1_u0 c7 <= ((not count(6) and not count(5) and not
count(4) and not count(3) and not count(2) and not count(1) and not
count(0)));
Note: Virtual equation for 'add_vi_ss_MODGEN_1_6' has been expanded (cost =
7):
add_vi_ss_MODGEN_1_6 <= ((not count(5) and count(6))
OR (not count(4) and count(6))
OR (not count(3) and count(6))
OR (not count(2) and count(6))
OR (not count(1) and count(6))
OR (not count(0) and count(6))
OR (not count(6) and count(5) and count(4) and count(3) and count(2) and
count(1) and count(0)));
Note: Virtual equation for 'sub_vi_ss_MODGEN_2_6' has been expanded (cost =
7):
sub_vi_ss_MODGEN_2_6 <= ((count(6) and count(5))
OR (count(6) and count(4))
OR (count(6) and count(3))
OR (count(6) and count(2))
OR (count(6) and count(1))
OR (count(6) and count(0))
OR (not count(6) and not count(5) and not count(4) and not count(3) and not
count(2) and not count(1) and not count(0)));
Substituting virtuals - pass 9:
Note: Virtual equation for 'MODULE_2_g2_a0_g1_z1_s0_g1_u0 c8' has been
expanded (cost = 3):
MODULE_2_g2_a0_g1_z1_s0_g1_u0 c8 <= ((count(7) and count(6) and count(5)
and count(4) and count(3) and count(2) and count(1) and count(0)));
Note: Virtual equation for 'MODULE_1_g2_a0_g1_z1_s0_g1_u0 c8' has been
expanded (cost = 3):
MODULE_1_g2_a0_g1_z1_s0_g1_u0 c8 <= ((not count(7) and not count(6) and not
count(5) and not count(4) and not count(3) and not count(2) and not count(1)
and not count(0)));
Note: Virtual equation for 'add_vi_ss_MODGEN_1_7' has been expanded (cost =
8):
add_vi_ss_MODGEN_1_7 <= ((not count(6) and count(7))
OR (not count(5) and count(7))
OR (not count(4) and count(7))
OR (not count(3) and count(7))
OR (not count(2) and count(7))
OR (not count(1) and count(7))
OR (not count(0) and count(7))
OR (not count(7) and count(6) and count(5) and count(4) and count(3) and
count(2) and count(1) and count(0)));
Note: Virtual equation for 'sub_vi_ss_MODGEN_2_7' has been expanded (cost =
8):
sub_vi_ss_MODGEN_2_7 <= ((count(7) and count(6))
OR (count(7) and count(5))
OR (count(7) and count(4))
OR (count(7) and count(3))
OR (count(7) and count(2))
OR (count(7) and count(1))
OR (count(7) and count(0))
OR (not count(7) and not count(6) and not count(5) and not count(4) and not
count(3) and not count(2) and not count(1) and not count(0)));
Substituting virtuals - pass 10:
Note: Virtual equation for 'MODULE_2_g2_a0_g1_z1_s0_g1_u0 c9' has been
expanded (cost = 2):
MODULE_2_g2_a0_g1_z1_s0_g1_u0 c9 <= ((count(8) and count(7) and count(6)
and count(5) and count(4) and count(3) and count(2) and count(1) and
count(0)));
Note: Virtual equation for 'MODULE_1_g2_a0_g1_z1_s0_g1_u0 c9' has been
expanded (cost = 2):
MODULE_1_g2_a0_g1_z1_s0_g1_u0 c9 <= ((not count(8) and not count(7) and not
count(6) and not count(5) and not count(4) and not count(3) and not count(2)
and not count(1) and not count(0)));
Note: Virtual equation for 'add_vi_ss_MODGEN_1_8' has been expanded (cost =
9):
add_vi_ss_MODGEN_1_8 <= ((not count(7) and count(8))
OR (not count(6) and count(8))
OR (not count(5) and count(8))
OR (not count(4) and count(8))
OR (not count(3) and count(8))
OR (not count(2) and count(8))
OR (not count(1) and count(8))
OR (not count(0) and count(8))
OR (not count(8) and count(7) and count(6) and count(5) and count(4) and
count(3) and count(2) and count(1) and count(0)));
Note: Virtual equation for 'sub_vi_ss_MODGEN_2_8' has been expanded (cost =
9):
sub_vi_ss_MODGEN_2_8 <= ((count(8) and count(7))
OR (count(8) and count(6))
OR (count(8) and count(5))
OR (count(8) and count(4))
OR (count(8) and count(3))
OR (count(8) and count(2))
OR (count(8) and count(1))
OR (count(8) and count(0))
OR (not count(8) and not count(7) and not count(6) and not count(5) and not
count(4) and not count(3) and not count(2) and not count(1) and not
count(0)));
Substituting virtuals - pass 11:
Note: Virtual equation for 'add_vi_ss_MODGEN_1_9' has been expanded (cost =
10):
add_vi_ss_MODGEN_1_9 <= ((not count(9) and count(8) and count(7) and
count(6) and count(5) and count(4) and count(3) and count(2) and count(1)
and count(0))
OR (not count(8) and count(9))
OR (not count(7) and count(9))
OR (not count(6) and count(9))
OR (not count(5) and count(9))
OR (not count(4) and count(9))
OR (not count(3) and count(9))
OR (not count(2) and count(9))
OR (not count(1) and count(9))
OR (not count(0) and count(9)));
Note: Virtual equation for 'sub_vi_ss_MODGEN_2_9' has been expanded (cost =
10):
sub_vi_ss_MODGEN_2_9 <= ((not count(9) and not count(8) and not count(7) and
not count(6) and not count(5) and not count(4) and not count(3) and not
count(2) and not count(1) and not count(0))
OR (count(9) and count(8))
OR (count(9) and count(7))
OR (count(9) and count(6))
OR (count(9) and count(5))
OR (count(9) and count(4))
OR (count(9) and count(3))
OR (count(9) and count(2))
OR (count(9) and count(1))
OR (count(9) and count(0)));
Substituting virtuals - pass 12:
----------------------------------------------------------
Circuit simplification results:
Expanded 39 signals.
Turned 0 signals into soft nodes.
Maximum expansion cost was set at 10.
----------------------------------------------------------
Created 134 PLD nodes.
Note: Removed unneeded node 'add_vi_ss_MODGEN_1_9'.
Note: Removed unneeded node 'sub_vi_ss_MODGEN_2_9'.
Note: Removed unneeded node 'add_vi_ss_MODGEN_1_8'.
Note: Removed unneeded node 'sub_vi_ss_MODGEN_2_8'.
Note: Removed unneeded node 'add_vi_ss_MODGEN_1_7'.
Note: Removed unneeded node 'sub_vi_ss_MODGEN_2_7'.
Note: Removed unneeded node 'add_vi_ss_MODGEN_1_6'.
Note: Removed unneeded node 'sub_vi_ss_MODGEN_2_6'.
Note: Removed unneeded node 'add_vi_ss_MODGEN_1_5'.
Note: Removed unneeded node 'sub_vi_ss_MODGEN_2_5'.
Note: Removed unneeded node 'add_vi_ss_MODGEN_1_4'.
Note: Removed unneeded node 'sub_vi_ss_MODGEN_2_4'.
Note: Removed unneeded node 'add_vi_ss_MODGEN_1_3'.
Note: Removed unneeded node 'sub_vi_ss_MODGEN_2_3'.
Note: Removed unneeded node 'add_vi_ss_MODGEN_1_2'.
Note: Removed unneeded node 'sub_vi_ss_MODGEN_2_2'.
Note: Removed unneeded node 'add_vi_ss_MODGEN_1_1'.
Note: Removed unneeded node 'sub_vi_ss_MODGEN_2_1'.
Note: Removed unneeded node 'add_vi_ss_MODGEN_1_0'.
Note: Removed unneeded node 'sub_vi_ss_MODGEN_2_0'.
Note: Removed unneeded node 'ile_8R'.
Note: Removed unneeded node 'ile_8S'.
Note: Removed unneeded node 'ile_7R'.
Note: Removed unneeded node 'ile_7S'.
Note: Removed unneeded node 'ile_6R'.
Note: Removed unneeded node 'ile_6S'.
Note: Removed unneeded node 'ile_5R'.
Note: Removed unneeded node 'ile_5S'.
Note: Removed unneeded node 'ile_4R'.
Note: Removed unneeded node 'ile_4S'.
Note: Removed unneeded node 'ile_3R'.
Note: Removed unneeded node 'ile_3S'.
Note: Removed unneeded node 'ile_2R'.
Note: Removed unneeded node 'ile_2S'.
Note: Removed unneeded node 'ile_1R'.
Note: Removed unneeded node 'ile_1S'.
Note: Removed unneeded node 'ile_0R'.
Note: Removed unneeded node 'ile_0S'.
Note: Removed unneeded node 'MODULE_1_g2_a0 d9'.
Note: Removed unneeded node 'MODULE_1_g2_a0 d8'.
Note: Removed unneeded node 'MODULE_1_g2_a0 d7'.
Note: Removed unneeded node 'MODULE_1_g2_a0 d6'.
Note: Removed unneeded node 'MODULE_1_g2_a0 d5'.
Note: Removed unneeded node 'MODULE_1_g2_a0 d4'.
Note: Removed unneeded node 'MODULE_1_g2_a0 d3'.
Note: Removed unneeded node 'MODULE_1_g2_a0 d2'.
Note: Removed unneeded node 'MODULE_1_g2_a0 d1'.
Note: Removed unneeded node 'MODULE_1_g2_a0 d0'.
Note: Removed unneeded node 'MODULE_1_g2_a0_g1_z1_s0_g1_u0 c9'.
Note: Removed unneeded node 'MODIN1_8'.
Note: Removed unneeded node 'MODULE_1_g2_a0_g1_z1_s0_g1_u0 c8'.
Note: Removed unneeded node 'MODIN1_9'.
Note: Removed unneeded node 'MODIN1_7'.
Note: Removed unneeded node 'MODULE_1_g2_a0_g1_z1_s0_g1_u0 c7'.
Note: Removed unneeded node 'MODIN1_6'.
Note: Removed unneeded node 'MODULE_1_g2_a0_g1_z1_s0_g1_u0 c6'.
Note: Removed unneeded node 'MODIN1_5'.
Note: Removed unneeded node 'MODULE_1_g2_a0_g1_z1_s0_g1_u0 c5'.
Note: Removed unneeded node 'MODIN1_4'.
Note: Removed unneeded node 'MODULE_1_g2_a0_g1_z1_s0_g1_u0 c4'.
Note: Removed unneeded node 'MODIN1_3'.
Note: Removed unneeded node 'MODULE_1_g2_a0_g1_z1_s0_g1_u0 c3'.
Note: Removed unneeded node 'MODIN1_2'.
Note: Removed unneeded node 'MODULE_1_g2_a0_g1_z1_s0_g1_u0 c2'.
Note: Removed unneeded node 'MODIN1_1'.
Note: Removed unneeded node 'MODULE_1_g2_a0_g1_z1_s0_g1_u0 c1'.
Note: Removed unneeded node 'MODIN1_0'.
Note: Removed unneeded node 'MODULE_1_g2_a0_g1_z1_s0_g1_u0 c0'.
Note: Removed unneeded node 'MODULE_2_g2_a0 s9'.
Note: Removed unneeded node 'MODULE_2_g2_a0 s8'.
Note: Removed unneeded node 'MODULE_2_g2_a0 s7'.
Note: Removed unneeded node 'MODULE_2_g2_a0 s6'.
Note: Removed unneeded node 'MODULE_2_g2_a0 s5'.
Note: Removed unneeded node 'MODULE_2_g2_a0 s4'.
Note: Removed unneeded node 'MODULE_2_g2_a0 s3'.
Note: Removed unneeded node 'MODULE_2_g2_a0 s2'.
Note: Removed unneeded node 'MODULE_2_g2_a0 s1'.
Note: Removed unneeded node 'MODULE_2_g2_a0 s0'.
Note: Removed unneeded node 'MODULE_2_g2_a0_g1_z1_s0_g1_u0 c9'.
Note: Removed unneeded node 'MODIN2_8'.
Note: Removed unneeded node 'MODULE_2_g2_a0_g1_z1_s0_g1_u0 c8'.
Note: Removed unneeded node 'MODIN2_9'.
Note: Removed unneeded node 'MODIN2_7'.
Note: Removed unneeded node 'MODULE_2_g2_a0_g1_z1_s0_g1_u0 c7'.
Note: Removed unneeded node 'MODIN2_6'.
Note: Removed unneeded node 'MODULE_2_g2_a0_g1_z1_s0_g1_u0 c6'.
Note: Removed unneeded node 'MODIN2_5'.
Note: Removed unneeded node 'MODULE_2_g2_a0_g1_z1_s0_g1_u0 c5'.
Note: Removed unneeded node 'MODIN2_4'.
Note: Removed unneeded node 'MODULE_2_g2_a0_g1_z1_s0_g1_u0 c4'.
Note: Removed unneeded node 'MODIN2_3'.
Note: Removed unneeded node 'MODULE_2_g2_a0_g1_z1_s0_g1_u0 c3'.
Note: Removed unneeded node 'MODIN2_2'.
Note: Removed unneeded node 'MODULE_2_g2_a0_g1_z1_s0_g1_u0 c2'.
Note: Removed unneeded node 'MODIN2_1'.
Note: Removed unneeded node 'MODULE_2_g2_a0_g1_z1_s0_g1_u0 c1'.
Note: Removed unneeded node 'MODIN2_0'.
Note: Removed unneeded node 'MODULE_2_g2_a0_g1_z1_s0_g1_u0 c0'.
Note: Removed unneeded node 'ile_9'.
Note: Removed unneeded node 'ile_8'.
Note: Removed unneeded node 'ile_7'.
Note: Removed unneeded node 'ile_6'.
Note: Removed unneeded node 'ile_5'.
Note: Removed unneeded node 'ile_4'.
Note: Removed unneeded node 'ile_3'.
Note: Removed unneeded node 'ile_2'.
Note: Removed unneeded node 'ile_1'.
Note: Removed unneeded node 'ile_0'.
Note: Removed unneeded node 'ile_9R'.
Note: Removed unneeded node 'ile_9S'.
C:\warp\bin\topld.exe: No errors.
----------------------------------------------------------------------------
PLD Optimizer Software: DSGNOPT.EXE 19 JUN1998 [v4.02 ] 4 IR x96
DESIGN HEADER INFORMATION (17:39:37)
Input File(s): gal0.pla
Device : C22V10
Package : PALCE22V10-7PC
ReportFile : gal0.rpt
Program Controls:
None.
Signal Requests:
GROUP DT-OPT ALL
GROUP FAST_SLEW ALL
Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software: DSGNOPT.EXE 19 JUN1998 [v4.02 ] 4 IR x96
OPTIMIZATION OPTIONS (17:39:37)
Messages:
Information: Process virtual 'ile_0D' ... expanded.
Information: Process virtual 'ile_1D' ... expanded.
Information: Process virtual 'ile_2D' ... expanded.
Information: Process virtual 'ile_3D' ... expanded.
Information: Process virtual 'ile_4D' ... expanded.
Information: Process virtual 'ile_5D' ... expanded.
Information: Process virtual 'ile_6D' ... expanded.
Information: Process virtual 'ile_7D' ... expanded.
Information: Process virtual 'ile_8D' ... expanded.
Information: Process virtual 'ile_9D' ... expanded.
Information: Optimizing logic using best output polarity for signals:
count(0).D count(1).D count(2).D count(3).D count(4).D count(5).D
count(6).D count(7).D count(8).D count(9).D
Information: Selected logic optimization OFF for signals:
count(0).AR count(0).C count(1).AR count(1).C count(2).AR
count(2).C
count(3).AR count(3).C count(4).AR count(4).C count(5).AR
count(5).C
count(6).AR count(6).C count(7).AR count(7).C count(8).AR
count(8).C
count(9).AR count(9).C
Summary:
Error Count = 0 Warning Count = 0
Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software: MINOPT.EXE 11 NOV97 [v4.02 ] 4 IR x90
LOGIC MINIMIZATION ()
Messages:
Summary:
Error Count = 0 Warning Count = 0
Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software: DSGNOPT.EXE 19 JUN1998 [v4.02 ] 4 IR x96
OPTIMIZATION OPTIONS (17:41:34)
Messages:
Information: Optimizing Banked Preset/Reset requirements.
Summary:
Error Count = 0 Warning Count = 0
Completed Successfully
----------------------------------------------------------------------------
PLD Compiler Software: PLA2JED.EXE 19 JUN1998 [v4.02 ] 4 IR x96
DESIGN EQUATIONS (17:41:34)
count(9).D =
/dir * enable * /count(2).Q * /count(1).Q * /count(0).Q *
/count(4).Q * /count(3).Q * /count(6).Q * /count(5).Q *
/count(7).Q * /count(8).Q * /count(9).Q
+ dir * enable * count(2).Q * count(1).Q * count(0).Q * count(4).Q *
count(3).Q * count(6).Q * count(5).Q * count(7).Q * count(8).Q *
/count(9).Q
+ /count(0).Q * count(8).Q * count(9).Q
+ count(0).Q * /count(7).Q * count(9).Q
+ count(2).Q * /count(1).Q * count(9).Q
+ count(1).Q * /count(3).Q * count(9).Q
+ /count(2).Q * count(4).Q * count(9).Q
+ count(3).Q * /count(5).Q * count(9).Q
+ /count(4).Q * count(6).Q * count(9).Q
+ /dir * count(5).Q * count(9).Q
+ /count(6).Q * count(7).Q * count(9).Q
+ dir * /count(8).Q * count(9).Q
+ /enable * count(9).Q
count(9).AR =
/reset_n
count(9).SP =
GND
count(9).C =
clk
count(8).D =
/dir * enable * /count(2).Q * /count(1).Q * /count(0).Q *
/count(4).Q * /count(3).Q * /count(6).Q * /count(5).Q *
/count(7).Q * /count(8).Q
+ dir * enable * count(2).Q * count(1).Q * count(0).Q * count(4).Q *
count(3).Q * count(6).Q * count(5).Q * count(7).Q * /count(8).Q
+ /count(0).Q * count(7).Q * count(8).Q
+ count(0).Q * /count(6).Q * count(8).Q
+ count(2).Q * /count(1).Q * count(8).Q
+ count(1).Q * /count(3).Q * count(8).Q
+ /count(2).Q * count(4).Q * count(8).Q
+ count(3).Q * /count(5).Q * count(8).Q
+ /count(4).Q * count(6).Q * count(8).Q
+ /dir * count(5).Q * count(8).Q
+ dir * /count(7).Q * count(8).Q
+ /enable * count(8).Q
count(8).AR =
/reset_n
count(8).SP =
GND
count(8).C =
clk
count(7).D =
/dir * enable * /count(2).Q * /count(1).Q * /count(0).Q *
/count(4).Q * /count(3).Q * /count(6).Q * /count(5).Q *
/count(7).Q
+ dir * enable * count(2).Q * count(1).Q * count(0).Q * count(4).Q *
count(3).Q * count(6).Q * count(5).Q * /count(7).Q
+ /count(0).Q * count(6).Q * count(7).Q
+ count(0).Q * /count(5).Q * count(7).Q
+ count(2).Q * /count(1).Q * count(7).Q
+ count(1).Q * /count(3).Q * count(7).Q
+ /count(2).Q * count(4).Q * count(7).Q
+ /dir * count(3).Q * count(7).Q
+ /count(4).Q * count(5).Q * count(7).Q
+ dir * /count(6).Q * count(7).Q
+ /enable * count(7).Q
count(7).AR =
/reset_n
count(7).SP =
GND
count(7).C =
clk
count(6).D =
/dir * enable * /count(2).Q * /count(1).Q * /count(0).Q *
/count(4).Q * /count(3).Q * /count(6).Q * /count(5).Q
+ dir * enable * count(2).Q * count(1).Q * count(0).Q * count(4).Q *
count(3).Q * /count(6).Q * count(5).Q
+ /count(0).Q * count(6).Q * count(5).Q
+ count(0).Q * /count(4).Q * count(6).Q
+ count(2).Q * /count(1).Q * count(6).Q
+ count(1).Q * /count(3).Q * count(6).Q
+ /count(2).Q * count(4).Q * count(6).Q
+ /dir * count(3).Q * count(6).Q
+ dir * count(6).Q * /count(5).Q
+ /enable * count(6).Q
count(6).AR =
/reset_n
count(6).SP =
GND
count(6).C =
clk
count(5).D =
/dir * enable * /count(2).Q * /count(1).Q * /count(0).Q *
/count(4).Q * /count(3).Q * /count(5).Q
+ dir * enable * count(2).Q * count(1).Q * count(0).Q * count(4).Q *
count(3).Q * /count(5).Q
+ /count(0).Q * count(4).Q * count(5).Q
+ count(0).Q * /count(3).Q * count(5).Q
+ count(2).Q * /count(1).Q * count(5).Q
+ /dir * count(1).Q * count(5).Q
+ /count(2).Q * count(3).Q * count(5).Q
+ dir * /count(4).Q * count(5).Q
+ /enable * count(5).Q
count(5).AR =
/reset_n
count(5).SP =
GND
count(5).C =
clk
count(4).D =
/dir * enable * /count(2).Q * /count(1).Q * /count(0).Q *
/count(4).Q * /count(3).Q
+ dir * enable * count(2).Q * count(1).Q * count(0).Q *
/count(4).Q * count(3).Q
+ /count(0).Q * count(4).Q * count(3).Q
+ /count(2).Q * count(0).Q * count(4).Q
+ count(2).Q * /count(1).Q * count(4).Q
+ /dir * count(1).Q * count(4).Q
+ dir * count(4).Q * /count(3).Q
+ /enable * count(4).Q
count(4).AR =
/reset_n
count(4).SP =
GND
count(4).C =
clk
count(3).D =
/dir * enable * /count(2).Q * /count(1).Q * /count(0).Q *
/count(3).Q
+ dir * enable * count(2).Q * count(1).Q * count(0).Q *
/count(3).Q
+ count(2).Q * /count(0).Q * count(3).Q
+ /count(1).Q * count(0).Q * count(3).Q
+ /dir * count(1).Q * count(3).Q
+ dir * /count(2).Q * count(3).Q
+ /enable * count(3).Q
count(3).AR =
/reset_n
count(3).SP =
GND
count(3).C =
clk
count(2).D =
/dir * enable * /count(2).Q * /count(1).Q * /count(0).Q
+ dir * enable * /count(2).Q * count(1).Q * count(0).Q
+ count(2).Q * count(1).Q * /count(0).Q
+ /dir * count(2).Q * count(0).Q
+ dir * count(2).Q * /count(1).Q
+ /enable * count(2).Q
count(2).AR =
/reset_n
count(2).SP =
GND
count(2).C =
clk
count(1).D =
/dir * enable * /count(1).Q * /count(0).Q
+ dir * enable * /count(1).Q * count(0).Q
+ dir * count(1).Q * /count(0).Q
+ /dir * count(1).Q * count(0).Q
+ /enable * count(1).Q
count(1).AR =
/reset_n
count(1).SP =
GND
count(1).C =
clk
count(0).D =
enable * /count(0).Q
+ /enable * count(0).Q
count(0).AR =
/reset_n
count(0).SP =
GND
count(0).C =
clk
Completed Successfully
----------------------------------------------------------------------------
PLD Compiler Software: PLA2JED.EXE 19 JUN1998 [v4.02 ] 4 IR x96
DESIGN RULE CHECK (17:41:34)
Messages:
None.
Summary:
Error Count = 0 Warning Count = 0
Completed Successfully
----------------------------------------------------------------------------
PLD Compiler Software: PLA2JED.EXE 19 JUN1998 [v4.02 ] 4 IR x96
DESIGN SIGNAL PLACEMENT (17:41:34)
Messages:
Information: Checking for duplicate NODE logic.
None.
C22V10
________________________________________
clk =| 1| |24|* not used
reset_n =| 2| |23|= count(3)
enable =| 3| |22|= count(5)
dir =| 4| |21|= count(7)
not used *| 5| |20|= count(2)
not used *| 6| |19|= count(0)
not used *| 7| |18|= count(1)
not used *| 8| |17|= count(9)
not used *| 9| |16|= count(8)
not used *|10| |15|= count(6)
not used *|11| |14|= count(4)
not used *|12| |13|* not used
________________________________________
Summary:
Error Count = 0 Warning Count = 0
Completed Successfully
----------------------------------------------------------------------------
PLD Compiler Software: PLA2JED.EXE 19 JUN1998 [v4.02 ] 4 IR x96
RESOURCE ALLOCATION (17:41:35)
Information: Macrocell Utilization.
Description Used Max
____________________________________
| Dedicated Inputs | 3 | 11 |
| Clock/Inputs | 1 | 1 |
| I/O Macrocells | 10 | 10 |
____________________________________
14 / 22 = 63 %
Information: Output Logic Product Term Utilization.
Node# Output Signal Name Used Max
______________________________________
| 14 | count(4) | 8 | 8 |
| 15 | count(6) | 10 | 10 |
| 16 | count(8) | 12 | 12 |
| 17 | count(9) | 13 | 14 |
| 18 | count(1) | 5 | 16 |
| 19 | count(0) | 2 | 16 |
| 20 | count(2) | 6 | 14 |
| 21 | count(7) | 11 | 12 |
| 22 | count(5) | 9 | 10 |
| 23 | count(3) | 7 | 8 |
| 25 | Unused | 0 | 1 |
______________________________________
83 / 121 = 68 %
Completed Successfully
----------------------------------------------------------------------------
PLD Compiler Software: PLA2JED.EXE 19 JUN1998 [v4.02 ] 4 IR x96
JEDEC ASSEMBLE (17:41:35)
Messages:
Information: Output file 'gal0.jed' created.
Summary:
Error Count = 0 Warning Count = 0
Completed Successfully at 17:41:35
From: "Juliusz" <juliusz_at_nospam_multi-ip.com.pl>
Subject: Re: GAL ... la la la ...
Date: Sun, 01 Aug 1999 21:18:39 GMT
Cypress C22V10 Jedec Fuse File: gal0.jed
This file was created on 07/31/1999 at 17:41:35
by PLA2JED.EXE 19 JUN1998 [v4.02 ] 4 IR x96
C22V10*
QP24* Number of Pins*
QF5828* Number of Fuses*
F0* Note: Default fuse setting 0*
G0* Note: Security bit Unprogrammed*
NOTE DEVICE C22V10*
NOTE PACKAGE PALCE22V10-7PC*
NOTE PINS clk:1 reset_n:2 enable:3 dir:4 count(4):14 count(6):15
count(8):16 *
NOTE PINS count(9):17 count(1):18 count(0):19 count(2):20 count(7):21 *
NOTE PINS count(5):22 count(3):23 *
NOTE PINS *
NOTE NODES *
L00000
11111011111111111111111111111111111111111111
- Node clk[1] => BANK : 1 *
L00044
11111111111111111111111111111111111111111111
11011111011110011101110111111111111111111111
11011111011101101110111011111111111111111111
11101111111111101101111111111111111111111111
11101111111111111110110111111111111111111111
11101111111110111111111011111111111111111111
11101111111101011111111111111111111111111111
11101111101111111111111111111111111111111111
00000000000000000000000000000000000000000000
- Node count(3)[23] => OE : 1 ,LOGIC : 8 *
L00440
11111111111111111111111111111111111111111111
11011101011110011101110111111111111111011111
11101101011101101110111011111111111111101111
11111110111111111101111111111111111111101111
11011110111111111110111111111111111111111111
11111110111111101111110111111111111111111111
11111110111110111111111011111111111111111111
11101110111111011111111111111111111111111111
11111110111101111111111111111111111111011111
11111110101111111111111111111111111111111111
00000000000000000000000000000000000000000000
- Node count(5)[22] => OE : 1 ,LOGIC : 10 *
L00924
11111111111111111111111111111111111111111111
11011101010110011101110111111111110111011111
11101110010101101110111011111111111011101111
11111111111011111101111111111111111011111111
11111101111011111110111111111111111111111111
11111111111011101111110111111111111111111111
11011111111011111111111011111111111111111111
11111111111011011111111111111111111111101111
11101111111010111111111111111111111111111111
11111110111011111111111111111111111111011111
11111111111001111111111111111111110111111111
11111111101011111111111111111111111111111111
00000000000000000000000000000000000000000000
- Node count(7)[21] => OE : 1 ,LOGIC : 12 *
L01496
11111111111111111111111111111111111111111111
11111111011110011101110111111111111111111111
11111111011101011110111011111111111111111111
11111111111111101101111011111111111111111111
11111111111110101110111111111111111111111111
11111111111101101111110111111111111111111111
11111111101111101111111111111111111111111111
00000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000
- Node count(2)[20] => OE : 1 ,LOGIC : 14 *
L02156
11111111111111111111111111111111111111111111
11111111011111111101111111111111111111111111
11111111101111111110111111111111111111111111
00000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000
- Node count(0)[19] => OE : 1 ,LOGIC : 16 *
L02904
11111111111111111111111111111111111111111111
11111111011110111101110111111111111111111111
11111111011101111110110111111111111111111111
11111111111101111101111011111111111111111111
11111111111110111110111011111111111111111111
11111111101111111111111011111111111111111111
00000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000
- Node count(1)[18] => OE : 1 ,LOGIC : 16 *
L03652
11111111111111111111111111111111111111111111
11011101010110011101110111011101110111011111
11101110011001101110111011011110111011101111
11111111111111111101111111101110111111111111
11111111110111111110111111101111111111111111
11111111111111101111110111101111111111111111
11011111111111111111111011101111111111111111
11111111111111011111111111101111111111101111
11101101111111111111111111101111111111111111
11111111111111111111111111101111111011011111
11111110111110111111111111101111111111111111
11111111111011111111111111101111110111111111
11111111111101111111111111101101111111111111
11111111101111111111111111101111111111111111
00000000000000000000000000000000000000000000
- Node count(9)[17] => OE : 1 ,LOGIC : 14 *
L04312
11111111111111111111111111111111111111111111
11011101010110011101110111111101110111011111
11101110011001101110111011111101111011101111
11111111111011111101111111111110111111111111
11111111111111111110111111111110110111111111
11111111111111101111110111111110111111111111
11011111111111111111111011111110111111111111
11111111111111011111111111111110111111101111
11101101111111111111111111111110111111111111
11111111111111111111111111111110111011011111
11111110111110111111111111111110111111111111
11111111110101111111111111111110111111111111
11111111101111111111111111111110111111111111
- Node count(8)[16] => OE : 1 ,LOGIC : 12 *
L04884
11111111111111111111111111111111111111111111
11011101011110011101110111111111110111011111
11101110011101101110111011111111110111101111
11111110111111111101111111111111111011111111
11111111111111111110111111111111111011011111
11111111111111101111110111111111111011111111
11011111111111111111111011111111111011111111
11111111111111011111111111111111111011101111
11101111111110111111111111111111111011111111
11111101111101111111111111111111111011111111
11111111101111111111111111111111111011111111
- Node count(6)[15] => OE : 1 ,LOGIC : 10 *
L05368
11111111111111111111111111111111111111111111
11011111011110011101110111111111111111011111
11101111011101101110111011111111111111011111
11101111111111111101111111111111111111101111
11111111111111011110111111111111111111101111
11111111111111101111110111111111111111101111
11111111111110111111111011111111111111101111
11011111111101111111111111111111111111101111
11111111101111111111111111111111111111101111
- Node count(4)[14] => OE : 1 ,LOGIC : 8 *
L05764
00000000000000000000000000000000000000000000
- Node reset_n[2] => BANK : 1 *
L05808
10* Note: 23 *
L05810
10* Note: 22 *
L05812
10* Note: 21 *
L05814
10* Note: 20 *
L05816
10* Note: 19 *
L05818
10* Note: 18 *
L05820
10* Note: 17 *
L05822
10* Note: 16 *
L05824
10* Note: 15 *
L05826
10* Note: 14 *
CC7FC* Note: Fuse Checksum*
995C
From: "Juliusz" <juliusz_at_nospam_multi-ip.com.pl>
Subject: Re: GAL ... la la la ...
Date: Sun, 01 Aug 1999 21:37:34 GMT
40 linijek programu i to ma byc trywialnie ?
Toz to rownania mniej zajmuja, a co dopiero makro :-)
A co trudne to ? Bawic sie jakimis toolsami na piechote ? A moze z TTL-i
skladac :-)
Nigdy wiecej:-)
68% to ponad 2/3 a nie ledwo ponad polowe :-)
zuzywasz tez 10 makrocel z 10, i 13 PT z 16 dostepnych.
Duzo wiecej sie nie zmiesci - zadnego wyjcia wolnego nie masz,
mozesz myslec o dodatkowych funkcjach licznika.
Np. wpis rownolegly. Watpie by zmiescilo sie np liczenie
w BCD a nie tylko binarnie.
Wiesz do tego to sa kostki po 23, 64 makrocele i wiecej :-). Zwykle najpierw
robi sie VHDL a na koniec zamawia scalaki :-) Byle nozki mialy identycznie.
Nie bierz tego za powaznie :-) To tylko przyklad :-) Zrobisz licznik 8
bitowy i juz 2 zostana wolne :-) Zawsze boli brak nozek w GAL-ach ale w CPLD
jest juz ich zwykle za duzo, bo polkniesz czasem tyle makrocel, ze nie pytaj
-)
Zrobilem kontroler DMA wspolpracujacy ze SRAM-em i magistrala ISA w VHDL-u
oczywiscie. Bedzie niebawem nowy produkt. Poszlo 119 ze 128 makrocelek i
ledwo sie zmiescilo uff. Sa trzy potezne maszyny stanow, pointery RAM i cala
logika arbitrazu pomiedzy ISA a tym co wchodzi gniazdem na sledziu i cala
elektronika wejsciowa. Chodzi na 4Megabity ! Czekam na plytki, zeby na
"czysto" poskladac ze 4 sztuki. He i zadnego procesora tym razem :-)
Problem z driverem - nawet pod linuxa tylko. Ja nie potrafie napisac, a inni
tez nie bardzo :-(
Juliusz