Analiza czasów opóźnień 10ns-24ns dla generowania VHDL w ALTERA i Cypress
Re: ALTERA i isp
From: "Juliusz" <juliusz_at_nospam_multi-ip.com.pl>
Subject: Re: ALTERA i isp
Date: Sun, 15 Aug 1999 19:30:03 GMT
A tu co kompilator wyplul:
Opoznienia sa od 10ns do max 24ns.
----------------------------------
| | | | | | |
_______________
-| |-
-| |-
-| |-
-| CYPRESS |-
-| |-
-| |- Warp VHDL Synthesis Compiler: Version 4 IR x90
-| |- Copyright (C) 1991, 1992, 1993,
| _____________| 1994, 1995, 1996, 1997 Cypress Semiconductor
| | | | | | |
======================================================================
Compiling: gal0.vhd
Options: -q -yv2 -yu -e10 -w100 -o2 -ygs -fO -fP -v10 -dc371i -pCY7C371I-
66AC gal0.vhd
======================================================================
C:\warp\bin\vhdlfe.exe V4 IR x90: VHDL parser
Sun Aug 15 20:37:23 1999
Library 'work' => directory 'lc371i'
Linking 'C:\warp\lib\common\work\cypress.vif'.
Library 'ieee' => directory 'C:\warp\lib\ieee\work'
Linking 'C:\warp\lib\ieee\work\stdlogic.vif'.
Library 'work' => directory 'lc371i'
Linking 'C:\warp\lib\common\stdlogic\lpmpkg.vif'.
Linking 'C:\warp\lib\common\stdlogic\rtlpkg.vif'.
Linking 'C:\warp\lib\common\stdlogic\mod_cnst.vif'.
Linking 'C:\warp\lib\common\stdlogic\mod_mth.vif'.
Linking 'C:\warp\lib\common\stdlogic\mod_gen.vif'.
gal0.vhd (line 35, col 31): Note: Substituting module 'cmp_vv_ss' for '='.
gal0.vhd (line 38, col 27): Note: Substituting module 'add_vi_ss' for '+'.
gal0.vhd (line 65, col 20): Note: Substituting module 'cmp_vv_ss' for '='.
gal0.vhd (line 65, col 38): Note: Substituting module 'cmp_vv_ss' for '='.
gal0.vhd (line 79, col 22): Note: Substituting module 'cmp_vv_ss' for '='.
gal0.vhd (line 79, col 42): Note: Substituting module 'cmp_vv_ss' for '='.
gal0.vhd (line 93, col 22): Note: Substituting module 'cmp_vv_ss' for '='.
gal0.vhd (line 93, col 42): Note: Substituting module 'cmp_vv_ss' for '='.
C:\warp\bin\vhdlfe.exe: No errors.
C:\warp\bin\tovif.exe V4 IR x90: High-level synthesis
Sun Aug 15 20:37:25 1999
Linking 'C:\warp\lib\common\work\cypress.vif'.
Linking 'C:\warp\lib\ieee\work\stdlogic.vif'.
Linking 'C:\warp\lib\common\stdlogic\lpmpkg.vif'.
Linking 'C:\warp\lib\common\stdlogic\rtlpkg.vif'.
Linking 'C:\warp\lib\common\stdlogic\mod_cnst.vif'.
Linking 'C:\warp\lib\common\stdlogic\mod_mth.vif'.
Linking 'C:\warp\lib\common\stdlogic\mod_gen.vif'.
Note: Removing wires from arch. 'generic_instance' of entity
'cmp_ss_generic1'.
Removing left side of wire: dataa(11) <= '0'.
Removing left side of wire: dataa(10) <= a(10).
Removing left side of wire: dataa(9) <= a(9).
Removing left side of wire: dataa(8) <= a(8).
Removing left side of wire: dataa(7) <= a(7).
Removing left side of wire: dataa(6) <= a(6).
Removing left side of wire: dataa(5) <= a(5).
Removing left side of wire: dataa(4) <= a(4).
Removing left side of wire: dataa(3) <= a(3).
Removing left side of wire: dataa(2) <= a(2).
Removing left side of wire: dataa(1) <= a(1).
Removing left side of wire: dataa(0) <= a(0).
Removing left side of wire: datab(11) <= b(0).
Removing left side of wire: datab(10) <= b(1).
Removing left side of wire: datab(9) <= b(2).
Removing left side of wire: datab(8) <= b(3).
Removing left side of wire: datab(7) <= b(4).
Removing left side of wire: datab(6) <= b(5).
Removing left side of wire: datab(5) <= b(6).
Removing left side of wire: datab(4) <= b(7).
Removing left side of wire: datab(3) <= b(8).
Removing left side of wire: datab(2) <= b(9).
Removing left side of wire: datab(1) <= b(10).
Removing left side of wire: datab(0) <= b(11).
Note: Removing wires from arch. 'generic_instance' of entity
'cmp_vv_ss_generic0'.
Note: Removing wires from arch. 'generic_instance' of entity
'cmp_ss_generic3'.
Removing left side of wire: dataa(11) <= '0'.
Removing left side of wire: dataa(10) <= a(10).
Removing left side of wire: dataa(9) <= a(9).
Removing left side of wire: dataa(8) <= a(8).
Removing left side of wire: dataa(7) <= a(7).
Removing left side of wire: dataa(6) <= a(6).
Removing left side of wire: dataa(5) <= a(5).
Removing left side of wire: dataa(4) <= a(4).
Removing left side of wire: dataa(3) <= a(3).
Removing left side of wire: dataa(2) <= a(2).
Removing left side of wire: dataa(1) <= a(1).
Removing left side of wire: dataa(0) <= a(0).
Removing left side of wire: datab(11) <= b(0).
Removing left side of wire: datab(10) <= b(1).
Removing left side of wire: datab(9) <= b(2).
Removing left side of wire: datab(8) <= b(3).
Removing left side of wire: datab(7) <= b(4).
Removing left side of wire: datab(6) <= b(5).
Removing left side of wire: datab(5) <= b(6).
Removing left side of wire: datab(4) <= b(7).
Removing left side of wire: datab(3) <= b(8).
Removing left side of wire: datab(2) <= b(9).
Removing left side of wire: datab(1) <= b(10).
Removing left side of wire: datab(0) <= b(11).
Note: Removing wires from arch. 'generic_instance' of entity
'cmp_vv_ss_generic2'.
Note: Removing wires from arch. 'generic_instance' of entity
'cmp_ss_generic5'.
Removing left side of wire: dataa(11) <= '0'.
Removing left side of wire: dataa(10) <= a(10).
Removing left side of wire: dataa(9) <= a(9).
Removing left side of wire: dataa(8) <= a(8).
Removing left side of wire: dataa(7) <= a(7).
Removing left side of wire: dataa(6) <= a(6).
Removing left side of wire: dataa(5) <= a(5).
Removing left side of wire: dataa(4) <= a(4).
Removing left side of wire: dataa(3) <= a(3).
Removing left side of wire: dataa(2) <= a(2).
Removing left side of wire: dataa(1) <= a(1).
Removing left side of wire: dataa(0) <= a(0).
Removing left side of wire: datab(11) <= b(0).
Removing left side of wire: datab(10) <= b(1).
Removing left side of wire: datab(9) <= b(2).
Removing left side of wire: datab(8) <= b(3).
Removing left side of wire: datab(7) <= b(4).
Removing left side of wire: datab(6) <= b(5).
Removing left side of wire: datab(5) <= b(6).
Removing left side of wire: datab(4) <= b(7).
Removing left side of wire: datab(3) <= b(8).
Removing left side of wire: datab(2) <= b(9).
Removing left side of wire: datab(1) <= b(10).
Removing left side of wire: datab(0) <= b(11).
Note: Removing wires from arch. 'generic_instance' of entity
'cmp_vv_ss_generic4'.
Note: Removing wires from arch. 'generic_instance' of entity
'cmp_ss_generic7'.
Removing left side of wire: dataa(11) <= '0'.
Removing left side of wire: dataa(10) <= a(10).
Removing left side of wire: dataa(9) <= a(9).
Removing left side of wire: dataa(8) <= a(8).
Removing left side of wire: dataa(7) <= a(7).
Removing left side of wire: dataa(6) <= a(6).
Removing left side of wire: dataa(5) <= a(5).
Removing left side of wire: dataa(4) <= a(4).
Removing left side of wire: dataa(3) <= a(3).
Removing left side of wire: dataa(2) <= a(2).
Removing left side of wire: dataa(1) <= a(1).
Removing left side of wire: dataa(0) <= a(0).
Removing left side of wire: datab(11) <= b(0).
Removing left side of wire: datab(10) <= b(1).
Removing left side of wire: datab(9) <= b(2).
Removing left side of wire: datab(8) <= b(3).
Removing left side of wire: datab(7) <= b(4).
Removing left side of wire: datab(6) <= b(5).
Removing left side of wire: datab(5) <= b(6).
Removing left side of wire: datab(4) <= b(7).
Removing left side of wire: datab(3) <= b(8).
Removing left side of wire: datab(2) <= b(9).
Removing left side of wire: datab(1) <= b(10).
Removing left side of wire: datab(0) <= b(11).
Note: Removing wires from arch. 'generic_instance' of entity
'cmp_vv_ss_generic6'.
Note: Removing wires from arch. 'generic_instance' of entity
'cmp_ss_generic9'.
Removing left side of wire: dataa(11) <= '0'.
Removing left side of wire: dataa(10) <= a(10).
Removing left side of wire: dataa(9) <= a(9).
Removing left side of wire: dataa(8) <= a(8).
Removing left side of wire: dataa(7) <= a(7).
Removing left side of wire: dataa(6) <= a(6).
Removing left side of wire: dataa(5) <= a(5).
Removing left side of wire: dataa(4) <= a(4).
Removing left side of wire: dataa(3) <= a(3).
Removing left side of wire: dataa(2) <= a(2).
Removing left side of wire: dataa(1) <= a(1).
Removing left side of wire: dataa(0) <= a(0).
Removing left side of wire: datab(11) <= b(0).
Removing left side of wire: datab(10) <= b(1).
Removing left side of wire: datab(9) <= b(2).
Removing left side of wire: datab(8) <= b(3).
Removing left side of wire: datab(7) <= b(4).
Removing left side of wire: datab(6) <= b(5).
Removing left side of wire: datab(5) <= b(6).
Removing left side of wire: datab(4) <= b(7).
Removing left side of wire: datab(3) <= b(8).
Removing left side of wire: datab(2) <= b(9).
Removing left side of wire: datab(1) <= b(10).
Removing left side of wire: datab(0) <= b(11).
Note: Removing wires from arch. 'generic_instance' of entity
'cmp_vv_ss_generic8'.
Note: Removing wires from arch. 'generic_instance' of entity
'finc_generic12'.
Removing left side of wire: b(0) <= cin.
Note: Removing wires from arch. 'generic_instance' of entity
'add_ss_generic11'.
Removing left side of wire: a(10) <= aa(10).
Removing left side of wire: a(9) <= aa(9).
Removing left side of wire: a(8) <= aa(8).
Removing left side of wire: a(7) <= aa(7).
Removing left side of wire: a(6) <= aa(6).
Removing left side of wire: a(5) <= aa(5).
Removing left side of wire: a(4) <= aa(4).
Removing left side of wire: a(3) <= aa(3).
Removing left side of wire: a(2) <= aa(2).
Removing left side of wire: a(1) <= aa(1).
Removing left side of wire: a(0) <= aa(0).
Removing left side of wire: b(10) <= bb(10).
Removing left side of wire: b(9) <= bb(9).
Removing left side of wire: b(8) <= bb(8).
Removing left side of wire: b(7) <= bb(7).
Removing left side of wire: b(6) <= bb(6).
Removing left side of wire: b(5) <= bb(5).
Removing left side of wire: b(4) <= bb(4).
Removing left side of wire: b(3) <= bb(3).
Removing left side of wire: b(2) <= bb(2).
Removing left side of wire: b(1) <= bb(1).
Removing left side of wire: b(0) <= bb(0).
Note: Removing wires from arch. 'generic_instance' of entity
'add_vi_ss_generic10'.
Removing left side of wire: b(10) <= '0'.
Removing left side of wire: b(9) <= '0'.
Removing left side of wire: b(8) <= '0'.
Removing left side of wire: b(7) <= '0'.
Removing left side of wire: b(6) <= '0'.
Removing left side of wire: b(5) <= '0'.
Removing left side of wire: b(4) <= '0'.
Removing left side of wire: b(3) <= '0'.
Removing left side of wire: b(2) <= '0'.
Removing left side of wire: b(1) <= '0'.
Removing left side of wire: b(0) <= '1'.
Note: Removing wires from arch. 'generic_instance' of entity
'cmp_ss_generic14'.
Removing left side of wire: dataa(10) <= a(10).
Removing left side of wire: dataa(9) <= a(9).
Removing left side of wire: dataa(8) <= a(8).
Removing left side of wire: dataa(7) <= a(7).
Removing left side of wire: dataa(6) <= a(6).
Removing left side of wire: dataa(5) <= a(5).
Removing left side of wire: dataa(4) <= a(4).
Removing left side of wire: dataa(3) <= a(3).
Removing left side of wire: dataa(2) <= a(2).
Removing left side of wire: dataa(1) <= a(1).
Removing left side of wire: dataa(0) <= a(0).
Removing left side of wire: datab(10) <= '0'.
Removing left side of wire: datab(9) <= '0'.
Removing left side of wire: datab(8) <= '0'.
Removing left side of wire: datab(7) <= '0'.
Removing left side of wire: datab(6) <= '0'.
Removing left side of wire: datab(5) <= '0'.
Removing left side of wire: datab(4) <= '0'.
Removing left side of wire: datab(3) <= b(0).
Removing left side of wire: datab(2) <= b(1).
Removing left side of wire: datab(1) <= b(2).
Removing left side of wire: datab(0) <= b(3).
Note: Removing wires from arch. 'generic_instance' of entity
'cmp_vv_ss_generic13'.
Note: Removing wires from arch. 'generic_instance' of entity
'cmp_ss_generic16'.
Removing left side of wire: dataa(10) <= a(10).
Removing left side of wire: dataa(9) <= a(9).
Removing left side of wire: dataa(8) <= a(8).
Removing left side of wire: dataa(7) <= a(7).
Removing left side of wire: dataa(6) <= a(6).
Removing left side of wire: dataa(5) <= a(5).
Removing left side of wire: dataa(4) <= a(4).
Removing left side of wire: dataa(3) <= a(3).
Removing left side of wire: dataa(2) <= a(2).
Removing left side of wire: dataa(1) <= a(1).
Removing left side of wire: dataa(0) <= a(0).
Removing left side of wire: datab(10) <= '0'.
Removing left side of wire: datab(9) <= '0'.
Removing left side of wire: datab(8) <= '0'.
Removing left side of wire: datab(7) <= '0'.
Removing left side of wire: datab(6) <= '0'.
Removing left side of wire: datab(5) <= '0'.
Removing left side of wire: datab(4) <= '0'.
Removing left side of wire: datab(3) <= b(0).
Removing left side of wire: datab(2) <= b(1).
Removing left side of wire: datab(1) <= b(2).
Removing left side of wire: datab(0) <= b(3).
Note: Removing wires from arch. 'generic_instance' of entity
'cmp_vv_ss_generic15'.
Note: Removing wires from arch. 'arch_piotrek' of entity 'piotrek'.
C:\warp\bin\tovif.exe: No errors.
C:\warp\bin\topld.exe V4 IR x96: Synthesis and optimization
Sun Aug 15 20:37:30 1999
Linking 'C:\warp\lib\common\work\cypress.vif'.
Linking 'C:\warp\lib\ieee\work\stdlogic.vif'.
Linking 'C:\warp\lib\common\stdlogic\lpmpkg.vif'.
Linking 'C:\warp\lib\common\stdlogic\rtlpkg.vif'.
Linking 'C:\warp\lib\common\stdlogic\mod_cnst.vif'.
Linking 'C:\warp\lib\common\stdlogic\mod_mth.vif'.
Linking 'C:\warp\lib\common\stdlogic\mod_gen.vif'.
Linking 'C:\warp\lib\lc370\stdlogic\c370.vif'.
----------------------------------------------------------
Detecting unused logic.
----------------------------------------------------------
------------------------------------------------------
Alias Detection
------------------------------------------------------
Aliasing licznik_9R to licznik_10R
Aliasing licznik_9S to licznik_10S
Aliasing licznik_8R to licznik_10R
Aliasing licznik_8S to licznik_10S
Aliasing licznik_7R to licznik_10R
Aliasing licznik_7S to licznik_10S
Aliasing licznik_6R to licznik_10R
Aliasing licznik_6S to licznik_10S
Aliasing licznik_5R to licznik_10R
Aliasing licznik_5S to licznik_10S
Aliasing licznik_4R to licznik_10R
Aliasing licznik_4S to licznik_10S
Aliasing licznik_3R to licznik_10R
Aliasing licznik_3S to licznik_10S
Aliasing licznik_2R to licznik_10R
Aliasing licznik_2S to licznik_10S
Aliasing licznik_1R to licznik_10R
Aliasing licznik_1S to licznik_10S
Aliasing licznik_0R to licznik_10R
Aliasing licznik_0S to licznik_10S
Aliasing adstartR to licznik_10R
Aliasing adstartS to licznik_10S
Aliasing s1R to licznik_10R
Aliasing s1S to licznik_10S
Aliasing s2R to licznik_10R
Aliasing s2S to licznik_10S
Aliasing s3R to licznik_10R
Aliasing s3S to licznik_10S
Aliasing MODIN1_2 to clk_4
Aliasing MODULE_2_g2_a0 eqa11 to MODULE_1_g2_a0 eqa11
Aliasing MODIN2_10 to MODIN1_10
Aliasing MODIN2_9 to MODIN1_9
Aliasing MODIN2_8 to MODIN1_8
Aliasing MODIN2_7 to MODIN1_7
Aliasing MODIN2_6 to MODIN1_6
Aliasing MODIN2_5 to MODIN1_5
Aliasing MODIN2_4 to MODIN1_4
Aliasing MODIN2_3 to MODIN1_3
Aliasing MODIN2_2 to clk_4
Aliasing MODIN2_1 to MODIN1_1
Aliasing MODIN2_0 to MODIN1_0
Aliasing MODULE_3_g2_a0 eqa11 to MODULE_1_g2_a0 eqa11
Aliasing MODIN3_10 to MODIN1_10
Aliasing MODIN3_9 to MODIN1_9
Aliasing MODIN3_8 to MODIN1_8
Aliasing MODIN3_7 to MODIN1_7
Aliasing MODIN3_6 to MODIN1_6
Aliasing MODIN3_5 to MODIN1_5
Aliasing MODIN3_4 to MODIN1_4
Aliasing MODIN3_3 to MODIN1_3
Aliasing MODIN3_2 to clk_4
Aliasing MODIN3_1 to MODIN1_1
Aliasing MODIN3_0 to MODIN1_0
Aliasing MODULE_4_g2_a0 eqa11 to MODULE_1_g2_a0 eqa11
Aliasing MODIN4_10 to MODIN1_10
Aliasing MODIN4_9 to MODIN1_9
Aliasing MODIN4_8 to MODIN1_8
Aliasing MODIN4_7 to MODIN1_7
Aliasing MODIN4_6 to MODIN1_6
Aliasing MODIN4_5 to MODIN1_5
Aliasing MODIN4_4 to MODIN1_4
Aliasing MODIN4_3 to MODIN1_3
Aliasing MODIN4_2 to clk_4
Aliasing MODIN4_1 to MODIN1_1
Aliasing MODIN4_0 to MODIN1_0
Aliasing MODULE_5_g2_a0 eqa11 to MODULE_1_g2_a0 eqa11
Aliasing MODIN5_10 to MODIN1_10
Aliasing MODIN5_9 to MODIN1_9
Aliasing MODIN5_8 to MODIN1_8
Aliasing MODIN5_7 to MODIN1_7
Aliasing MODIN5_6 to MODIN1_6
Aliasing MODIN5_5 to MODIN1_5
Aliasing MODIN5_4 to MODIN1_4
Aliasing MODIN5_3 to MODIN1_3
Aliasing MODIN5_2 to clk_4
Aliasing MODIN5_1 to MODIN1_1
Aliasing MODIN5_0 to MODIN1_0
Aliasing MODIN6_9 to MODIN1_9
Aliasing MODIN6_10 to MODIN1_10
Aliasing MODIN6_8 to MODIN1_8
Aliasing MODIN6_7 to MODIN1_7
Aliasing MODIN6_6 to MODIN1_6
Aliasing MODIN6_5 to MODIN1_5
Aliasing MODIN6_4 to MODIN1_4
Aliasing MODIN6_3 to MODIN1_3
Aliasing MODIN6_2 to clk_4
Aliasing MODIN6_1 to MODIN1_1
Aliasing MODIN6_0 to MODIN1_0
Aliasing MODULE_6_g2_a0_g1_z1_s0_g1_u0 c0 to MODULE_1_g2_a0 eqa11
Aliasing MODIN7_10 to MODIN1_10
Aliasing MODIN7_9 to MODIN1_9
Aliasing MODIN7_8 to MODIN1_8
Aliasing MODIN7_7 to MODIN1_7
Aliasing MODIN7_6 to MODIN1_6
Aliasing MODIN7_5 to MODIN1_5
Aliasing MODIN7_4 to MODIN1_4
Aliasing MODIN7_3 to MODIN1_3
Aliasing MODIN7_2 to clk_4
Aliasing MODIN7_1 to MODIN1_1
Aliasing MODIN7_0 to MODIN1_0
Aliasing MODIN8_10 to MODIN1_10
Aliasing MODIN8_9 to MODIN1_9
Aliasing MODIN8_8 to MODIN1_8
Aliasing MODIN8_7 to MODIN1_7
Aliasing MODIN8_6 to MODIN1_6
Aliasing MODIN8_5 to MODIN1_5
Aliasing MODIN8_4 to MODIN1_4
Aliasing MODIN8_3 to MODIN1_3
Aliasing MODIN8_2 to clk_4
Aliasing MODIN8_1 to MODIN1_1
Aliasing MODIN8_0 to MODIN1_0
Removing Rhs of wire clk_4[2] = licznik_2[24]
Removing Rhs of wire cmp_vv_ss_MODGEN_1[8] = MODULE_1_g2_a0 eqa0[87]
Removing Rhs of wire add_vi_ss_MODGEN_2_10[9] = MODULE_6_g2_a0 s10[181]
Removing Rhs of wire add_vi_ss_MODGEN_2_9[11] = MODULE_6_g2_a0 s9[182]
Removing Rhs of wire add_vi_ss_MODGEN_2_8[13] = MODULE_6_g2_a0 s8[183]
Removing Rhs of wire add_vi_ss_MODGEN_2_7[15] = MODULE_6_g2_a0 s7[184]
Removing Rhs of wire add_vi_ss_MODGEN_2_6[17] = MODULE_6_g2_a0 s6[185]
Removing Rhs of wire add_vi_ss_MODGEN_2_5[19] = MODULE_6_g2_a0 s5[186]
Removing Rhs of wire add_vi_ss_MODGEN_2_4[21] = MODULE_6_g2_a0 s4[187]
Removing Rhs of wire add_vi_ss_MODGEN_2_3[23] = MODULE_6_g2_a0 s3[188]
Removing Rhs of wire add_vi_ss_MODGEN_2_2[25] = MODULE_6_g2_a0 s2[189]
Removing Rhs of wire add_vi_ss_MODGEN_2_1[27] = MODULE_6_g2_a0 s1[190]
Removing Rhs of wire add_vi_ss_MODGEN_2_0[29] = MODULE_6_g2_a0 s0[191]
Removing Lhs of wire licznik_9R[32] = licznik_10R[30]
Removing Lhs of wire licznik_9S[33] = licznik_10S[31]
Removing Lhs of wire licznik_8R[34] = licznik_10R[30]
Removing Lhs of wire licznik_8S[35] = licznik_10S[31]
Removing Lhs of wire licznik_7R[36] = licznik_10R[30]
Removing Lhs of wire licznik_7S[37] = licznik_10S[31]
Removing Lhs of wire licznik_6R[38] = licznik_10R[30]
Removing Lhs of wire licznik_6S[39] = licznik_10S[31]
Removing Lhs of wire licznik_5R[40] = licznik_10R[30]
Removing Lhs of wire licznik_5S[41] = licznik_10S[31]
Removing Lhs of wire licznik_4R[42] = licznik_10R[30]
Removing Lhs of wire licznik_4S[43] = licznik_10S[31]
Removing Lhs of wire licznik_3R[44] = licznik_10R[30]
Removing Lhs of wire licznik_3S[45] = licznik_10S[31]
Removing Lhs of wire licznik_2R[46] = licznik_10R[30]
Removing Lhs of wire licznik_2S[47] = licznik_10S[31]
Removing Lhs of wire licznik_1R[48] = licznik_10R[30]
Removing Lhs of wire licznik_1S[49] = licznik_10S[31]
Removing Lhs of wire licznik_0R[50] = licznik_10R[30]
Removing Lhs of wire licznik_0S[51] = licznik_10S[31]
Removing Lhs of wire adstartR[52] = licznik_10R[30]
Removing Lhs of wire adstartS[53] = licznik_10S[31]
Removing Rhs of wire cmp_vv_ss_MODGEN_3[54] = MODULE_7_g2_a0 eqa0[234]
Removing Rhs of wire cmp_vv_ss_MODGEN_4[55] = MODULE_8_g2_a0 eqa0[256]
Removing Lhs of wire s1R[56] = licznik_10R[30]
Removing Lhs of wire s1S[57] = licznik_10S[31]
Removing Rhs of wire cmp_vv_ss_MODGEN_5[58] = MODULE_2_g2_a0 eqa0[110]
Removing Rhs of wire cmp_vv_ss_MODGEN_6[59] = MODULE_4_g2_a0 eqa0[156]
Removing Lhs of wire s2R[60] = licznik_10R[30]
Removing Lhs of wire s2S[61] = licznik_10S[31]
Removing Rhs of wire cmp_vv_ss_MODGEN_7[62] = MODULE_3_g2_a0 eqa0[133]
Removing Rhs of wire cmp_vv_ss_MODGEN_8[63] = MODULE_5_g2_a0 eqa0[179]
Removing Lhs of wire s3R[64] = licznik_10R[30]
Removing Lhs of wire s3S[65] = licznik_10S[31]
Removing Lhs of wire MODIN1_10[68] = licznik_10[7]
Removing Lhs of wire MODIN1_9[70] = licznik_9[10]
Removing Lhs of wire MODIN1_8[72] = licznik_8[12]
Removing Lhs of wire MODIN1_7[74] = licznik_7[14]
Removing Lhs of wire MODIN1_6[76] = licznik_6[16]
Removing Lhs of wire MODIN1_5[78] = licznik_5[18]
Removing Lhs of wire MODIN1_4[80] = licznik_4[20]
Removing Lhs of wire MODIN1_3[82] = licznik_3[22]
Removing Lhs of wire MODIN1_2[84] = clk_4[2]
Removing Lhs of wire MODIN1_1[86] = licznik_1[26]
Removing Lhs of wire MODIN1_0[88] = licznik_0[28]
Removing Lhs of wire MODULE_2_g2_a0 eqa11[89] = MODULE_1_g2_a0 eqa11[66]
Removing Lhs of wire MODIN2_10[91] = licznik_10[7]
Removing Lhs of wire MODIN2_9[93] = licznik_9[10]
Removing Lhs of wire MODIN2_8[95] = licznik_8[12]
Removing Lhs of wire MODIN2_7[97] = licznik_7[14]
Removing Lhs of wire MODIN2_6[99] = licznik_6[16]
Removing Lhs of wire MODIN2_5[101] = licznik_5[18]
Removing Lhs of wire MODIN2_4[103] = licznik_4[20]
Removing Lhs of wire MODIN2_3[105] = licznik_3[22]
Removing Lhs of wire MODIN2_2[107] = clk_4[2]
Removing Lhs of wire MODIN2_1[109] = licznik_1[26]
Removing Lhs of wire MODIN2_0[111] = licznik_0[28]
Removing Lhs of wire MODULE_3_g2_a0 eqa11[112] = MODULE_1_g2_a0 eqa11[66]
Removing Lhs of wire MODIN3_10[114] = licznik_10[7]
Removing Lhs of wire MODIN3_9[116] = licznik_9[10]
Removing Lhs of wire MODIN3_8[118] = licznik_8[12]
Removing Lhs of wire MODIN3_7[120] = licznik_7[14]
Removing Lhs of wire MODIN3_6[122] = licznik_6[16]
Removing Lhs of wire MODIN3_5[124] = licznik_5[18]
Removing Lhs of wire MODIN3_4[126] = licznik_4[20]
Removing Lhs of wire MODIN3_3[128] = licznik_3[22]
Removing Lhs of wire MODIN3_2[130] = clk_4[2]
Removing Lhs of wire MODIN3_1[132] = licznik_1[26]
Removing Lhs of wire MODIN3_0[134] = licznik_0[28]
Removing Lhs of wire MODULE_4_g2_a0 eqa11[135] = MODULE_1_g2_a0 eqa11[66]
Removing Lhs of wire MODIN4_10[137] = licznik_10[7]
Removing Lhs of wire MODIN4_9[139] = licznik_9[10]
Removing Lhs of wire MODIN4_8[141] = licznik_8[12]
Removing Lhs of wire MODIN4_7[143] = licznik_7[14]
Removing Lhs of wire MODIN4_6[145] = licznik_6[16]
Removing Lhs of wire MODIN4_5[147] = licznik_5[18]
Removing Lhs of wire MODIN4_4[149] = licznik_4[20]
Removing Lhs of wire MODIN4_3[151] = licznik_3[22]
Removing Lhs of wire MODIN4_2[153] = clk_4[2]
Removing Lhs of wire MODIN4_1[155] = licznik_1[26]
Removing Lhs of wire MODIN4_0[157] = licznik_0[28]
Removing Lhs of wire MODULE_5_g2_a0 eqa11[158] = MODULE_1_g2_a0 eqa11[66]
Removing Lhs of wire MODIN5_10[160] = licznik_10[7]
Removing Lhs of wire MODIN5_9[162] = licznik_9[10]
Removing Lhs of wire MODIN5_8[164] = licznik_8[12]
Removing Lhs of wire MODIN5_7[166] = licznik_7[14]
Removing Lhs of wire MODIN5_6[168] = licznik_6[16]
Removing Lhs of wire MODIN5_5[170] = licznik_5[18]
Removing Lhs of wire MODIN5_4[172] = licznik_4[20]
Removing Lhs of wire MODIN5_3[174] = licznik_3[22]
Removing Lhs of wire MODIN5_2[176] = clk_4[2]
Removing Lhs of wire MODIN5_1[178] = licznik_1[26]
Removing Lhs of wire MODIN5_0[180] = licznik_0[28]
Removing Lhs of wire MODIN6_9[193] = licznik_9[10]
Removing Lhs of wire MODIN6_10[195] = licznik_10[7]
Removing Lhs of wire MODIN6_8[196] = licznik_8[12]
Removing Lhs of wire MODIN6_7[198] = licznik_7[14]
Removing Lhs of wire MODIN6_6[200] = licznik_6[16]
Removing Lhs of wire MODIN6_5[202] = licznik_5[18]
Removing Lhs of wire MODIN6_4[204] = licznik_4[20]
Removing Lhs of wire MODIN6_3[206] = licznik_3[22]
Removing Lhs of wire MODIN6_2[208] = clk_4[2]
Removing Lhs of wire MODIN6_1[210] = licznik_1[26]
Removing Lhs of wire MODIN6_0[212] = licznik_0[28]
Removing Lhs of wire MODULE_6_g2_a0_g1_z1_s0_g1_u0 c0[213] =
MODULE_1_g2_a0 eqa11[66]
Removing Lhs of wire MODIN7_10[215] = licznik_10[7]
Removing Lhs of wire MODIN7_9[217] = licznik_9[10]
Removing Lhs of wire MODIN7_8[219] = licznik_8[12]
Removing Lhs of wire MODIN7_7[221] = licznik_7[14]
Removing Lhs of wire MODIN7_6[223] = licznik_6[16]
Removing Lhs of wire MODIN7_5[225] = licznik_5[18]
Removing Lhs of wire MODIN7_4[227] = licznik_4[20]
Removing Lhs of wire MODIN7_3[229] = licznik_3[22]
Removing Lhs of wire MODIN7_2[231] = clk_4[2]
Removing Lhs of wire MODIN7_1[233] = licznik_1[26]
Removing Lhs of wire MODIN7_0[235] = licznik_0[28]
Removing Lhs of wire MODIN8_10[237] = licznik_10[7]
Removing Lhs of wire MODIN8_9[239] = licznik_9[10]
Removing Lhs of wire MODIN8_8[241] = licznik_8[12]
Removing Lhs of wire MODIN8_7[243] = licznik_7[14]
Removing Lhs of wire MODIN8_6[245] = licznik_6[16]
Removing Lhs of wire MODIN8_5[247] = licznik_5[18]
Removing Lhs of wire MODIN8_4[249] = licznik_4[20]
Removing Lhs of wire MODIN8_3[251] = licznik_3[22]
Removing Lhs of wire MODIN8_2[253] = clk_4[2]
Removing Lhs of wire MODIN8_1[255] = licznik_1[26]
Removing Lhs of wire MODIN8_0[257] = licznik_0[28]
------------------------------------------------------
Aliased 0 equations, 140 wires.
------------------------------------------------------
----------------------------------------------------------
Circuit simplification
----------------------------------------------------------
Substituting virtuals - pass 1:
Note: Virtual equation for 'MODULE_1_g2_a0 eqa11' has been expanded (cost
= 0):
MODULE_1_g2_a0 eqa11 <= ('1') ;
Note: Virtual equation for 'MODULE_1_g2_a0 eqa10' has been expanded (cost
= 0):
MODULE_1_g2_a0 eqa10 <= (licznik_10);
Note: Virtual equation for 'MODULE_1_g2_a0 eqa9' has been expanded (cost =
1):
MODULE_1_g2_a0 eqa9 <= ((not licznik_9 and licznik_10));
Note: Virtual equation for 'MODULE_1_g2_a0 eqa8' has been expanded (cost =
1):
MODULE_1_g2_a0 eqa8 <= ((not licznik_9 and not licznik_8 and licznik_10));
Note: Virtual equation for 'MODULE_1_g2_a0 eqa7' has been expanded (cost =
1):
MODULE_1_g2_a0 eqa7 <= ((not licznik_9 and not licznik_8 and licznik_10 and
licznik_7));
Note: Virtual equation for 'MODULE_1_g2_a0 eqa6' has been expanded (cost =
1):
MODULE_1_g2_a0 eqa6 <= ((not licznik_9 and not licznik_8 and licznik_10 and
licznik_7 and licznik_6));
Note: Virtual equation for 'MODULE_1_g2_a0 eqa5' has been expanded (cost =
1):
MODULE_1_g2_a0 eqa5 <= ((not licznik_9 and not licznik_8 and not licznik_5
and licznik_10 and licznik_7 and licznik_6));
Note: Virtual equation for 'MODULE_1_g2_a0 eqa4' has been expanded (cost =
1):
MODULE_1_g2_a0 eqa4 <= ((not licznik_9 and not licznik_8 and not licznik_5
and not licznik_4 and licznik_10 and licznik_7 and licznik_6));
Note: Virtual equation for 'MODULE_1_g2_a0 eqa3' has been expanded (cost =
1):
MODULE_1_g2_a0 eqa3 <= ((not licznik_9 and not licznik_8 and not licznik_5
and not licznik_4 and licznik_10 and licznik_7 and licznik_6 and
licznik_3));
Note: Virtual equation for 'MODULE_1_g2_a0 eqa2' has been expanded (cost =
1):
MODULE_1_g2_a0 eqa2 <= ((not clk_4 and not licznik_9 and not licznik_8 and
not licznik_5 and not licznik_4 and licznik_10 and licznik_7 and licznik_6
and licznik_3));
Note: Virtual equation for 'MODULE_2_g2_a0 eqa10' has been expanded (cost
= 0):
MODULE_2_g2_a0 eqa10 <= (not licznik_10);
Note: Virtual equation for 'MODULE_2_g2_a0 eqa9' has been expanded (cost =
1):
MODULE_2_g2_a0 eqa9 <= ((not licznik_10 and not licznik_9));
Note: Virtual equation for 'MODULE_2_g2_a0 eqa8' has been expanded (cost =
1):
MODULE_2_g2_a0 eqa8 <= ((not licznik_10 and not licznik_9 and licznik_8));
Note: Virtual equation for 'MODULE_2_g2_a0 eqa7' has been expanded (cost =
1):
MODULE_2_g2_a0 eqa7 <= ((not licznik_10 and not licznik_9 and licznik_8 and
licznik_7));
Note: Virtual equation for 'MODULE_2_g2_a0 eqa6' has been expanded (cost =
1):
MODULE_2_g2_a0 eqa6 <= ((not licznik_10 and not licznik_9 and not licznik_6
and licznik_8 and licznik_7));
Note: Virtual equation for 'MODULE_2_g2_a0 eqa5' has been expanded (cost =
1):
MODULE_2_g2_a0 eqa5 <= ((not licznik_10 and not licznik_9 and not licznik_6
and not licznik_5 and licznik_8 and licznik_7));
Note: Virtual equation for 'MODULE_2_g2_a0 eqa4' has been expanded (cost =
1):
MODULE_2_g2_a0 eqa4 <= ((not licznik_10 and not licznik_9 and not licznik_6
and not licznik_5 and licznik_8 and licznik_7 and licznik_4));
Note: Virtual equation for 'MODULE_2_g2_a0 eqa3' has been expanded (cost =
1):
MODULE_2_g2_a0 eqa3 <= ((not licznik_10 and not licznik_9 and not licznik_6
and not licznik_5 and licznik_8 and licznik_7 and licznik_4 and licznik_3));
Note: Virtual equation for 'MODULE_2_g2_a0 eqa2' has been expanded (cost =
1):
MODULE_2_g2_a0 eqa2 <= ((not clk_4 and not licznik_10 and not licznik_9 and
not licznik_6 and not licznik_5 and licznik_8 and licznik_7 and licznik_4
and licznik_3));
Note: Virtual equation for 'MODULE_3_g2_a0 eqa10' has been expanded (cost
= 0):
MODULE_3_g2_a0 eqa10 <= (not licznik_10);
Note: Virtual equation for 'MODULE_3_g2_a0 eqa9' has been expanded (cost =
1):
MODULE_3_g2_a0 eqa9 <= ((not licznik_10 and licznik_9));
Note: Virtual equation for 'MODULE_3_g2_a0 eqa8' has been expanded (cost =
1):
MODULE_3_g2_a0 eqa8 <= ((not licznik_10 and licznik_9 and licznik_8));
Note: Virtual equation for 'MODULE_3_g2_a0 eqa7' has been expanded (cost =
1):
MODULE_3_g2_a0 eqa7 <= ((not licznik_10 and not licznik_7 and licznik_9 and
licznik_8));
Note: Virtual equation for 'MODULE_3_g2_a0 eqa6' has been expanded (cost =
1):
MODULE_3_g2_a0 eqa6 <= ((not licznik_10 and not licznik_7 and not licznik_6
and licznik_9 and licznik_8));
Note: Virtual equation for 'MODULE_3_g2_a0 eqa5' has been expanded (cost =
1):
MODULE_3_g2_a0 eqa5 <= ((not licznik_10 and not licznik_7 and not licznik_6
and licznik_9 and licznik_8 and licznik_5));
Note: Virtual equation for 'MODULE_3_g2_a0 eqa4' has been expanded (cost =
1):
MODULE_3_g2_a0 eqa4 <= ((not licznik_10 and not licznik_7 and not licznik_6
and licznik_9 and licznik_8 and licznik_5 and licznik_4));
Note: Virtual equation for 'MODULE_3_g2_a0 eqa3' has been expanded (cost =
1):
MODULE_3_g2_a0 eqa3 <= ((not licznik_10 and not licznik_7 and not licznik_6
and not licznik_3 and licznik_9 and licznik_8 and licznik_5 and licznik_4));
Note: Virtual equation for 'MODULE_3_g2_a0 eqa2' has been expanded (cost =
1):
MODULE_3_g2_a0 eqa2 <= ((not clk_4 and not licznik_10 and not licznik_7 and
not licznik_6 and not licznik_3 and licznik_9 and licznik_8 and licznik_5
and licznik_4));
Note: Virtual equation for 'MODULE_4_g2_a0 eqa10' has been expanded (cost
= 0):
MODULE_4_g2_a0 eqa10 <= (not licznik_10);
Note: Virtual equation for 'MODULE_4_g2_a0 eqa9' has been expanded (cost =
1):
MODULE_4_g2_a0 eqa9 <= ((not licznik_10 and not licznik_9));
Note: Virtual equation for 'MODULE_4_g2_a0 eqa8' has been expanded (cost =
1):
MODULE_4_g2_a0 eqa8 <= ((not licznik_10 and not licznik_9 and licznik_8));
Note: Virtual equation for 'MODULE_4_g2_a0 eqa7' has been expanded (cost =
1):
MODULE_4_g2_a0 eqa7 <= ((not licznik_10 and not licznik_9 and licznik_8 and
licznik_7));
Note: Virtual equation for 'MODULE_4_g2_a0 eqa6' has been expanded (cost =
1):
MODULE_4_g2_a0 eqa6 <= ((not licznik_10 and not licznik_9 and not licznik_6
and licznik_8 and licznik_7));
Note: Virtual equation for 'MODULE_4_g2_a0 eqa5' has been expanded (cost =
1):
MODULE_4_g2_a0 eqa5 <= ((not licznik_10 and not licznik_9 and not licznik_6
and not licznik_5 and licznik_8 and licznik_7));
Note: Virtual equation for 'MODULE_4_g2_a0 eqa4' has been expanded (cost =
1):
MODULE_4_g2_a0 eqa4 <= ((not licznik_10 and not licznik_9 and not licznik_6
and not licznik_5 and licznik_8 and licznik_7 and licznik_4));
Note: Virtual equation for 'MODULE_4_g2_a0 eqa3' has been expanded (cost =
1):
MODULE_4_g2_a0 eqa3 <= ((not licznik_10 and not licznik_9 and not licznik_6
and not licznik_5 and licznik_8 and licznik_7 and licznik_4 and licznik_3));
Note: Virtual equation for 'MODULE_4_g2_a0 eqa2' has been expanded (cost =
1):
MODULE_4_g2_a0 eqa2 <= ((not clk_4 and not licznik_10 and not licznik_9 and
not licznik_6 and not licznik_5 and licznik_8 and licznik_7 and licznik_4
and licznik_3));
Note: Virtual equation for 'MODULE_5_g2_a0 eqa10' has been expanded (cost
= 0):
MODULE_5_g2_a0 eqa10 <= (not licznik_10);
Note: Virtual equation for 'MODULE_5_g2_a0 eqa9' has been expanded (cost =
1):
MODULE_5_g2_a0 eqa9 <= ((not licznik_10 and licznik_9));
Note: Virtual equation for 'MODULE_5_g2_a0 eqa8' has been expanded (cost =
1):
MODULE_5_g2_a0 eqa8 <= ((not licznik_10 and licznik_9 and licznik_8));
Note: Virtual equation for 'MODULE_5_g2_a0 eqa7' has been expanded (cost =
1):
MODULE_5_g2_a0 eqa7 <= ((not licznik_10 and not licznik_7 and licznik_9 and
licznik_8));
Note: Virtual equation for 'MODULE_5_g2_a0 eqa6' has been expanded (cost =
1):
MODULE_5_g2_a0 eqa6 <= ((not licznik_10 and not licznik_7 and not licznik_6
and licznik_9 and licznik_8));
Note: Virtual equation for 'MODULE_5_g2_a0 eqa5' has been expanded (cost =
1):
MODULE_5_g2_a0 eqa5 <= ((not licznik_10 and not licznik_7 and not licznik_6
and licznik_9 and licznik_8 and licznik_5));
Note: Virtual equation for 'MODULE_5_g2_a0 eqa4' has been expanded (cost =
1):
MODULE_5_g2_a0 eqa4 <= ((not licznik_10 and not licznik_7 and not licznik_6
and licznik_9 and licznik_8 and licznik_5 and licznik_4));
Note: Virtual equation for 'MODULE_5_g2_a0 eqa3' has been expanded (cost =
1):
MODULE_5_g2_a0 eqa3 <= ((not licznik_10 and not licznik_7 and not licznik_6
and not licznik_3 and licznik_9 and licznik_8 and licznik_5 and licznik_4));
Note: Virtual equation for 'MODULE_5_g2_a0 eqa2' has been expanded (cost =
1):
MODULE_5_g2_a0 eqa2 <= ((not clk_4 and not licznik_10 and not licznik_7 and
not licznik_6 and not licznik_3 and licznik_9 and licznik_8 and licznik_5
and licznik_4));
Note: Virtual equation for 'MODULE_7_g2_a0 eqa10' has been expanded (cost
= 0):
MODULE_7_g2_a0 eqa10 <= (not licznik_10);
Note: Virtual equation for 'MODULE_7_g2_a0 eqa9' has been expanded (cost =
1):
MODULE_7_g2_a0 eqa9 <= ((not licznik_10 and not licznik_9));
Note: Virtual equation for 'MODULE_7_g2_a0 eqa8' has been expanded (cost =
1):
MODULE_7_g2_a0 eqa8 <= ((not licznik_10 and not licznik_9 and not
licznik_8));
Note: Virtual equation for 'MODULE_7_g2_a0 eqa7' has been expanded (cost =
1):
MODULE_7_g2_a0 eqa7 <= ((not licznik_10 and not licznik_9 and not licznik_8
and not licznik_7));
Note: Virtual equation for 'MODULE_7_g2_a0 eqa6' has been expanded (cost =
1):
MODULE_7_g2_a0 eqa6 <= ((not licznik_10 and not licznik_9 and not licznik_8
and not licznik_7 and not licznik_6));
Note: Virtual equation for 'MODULE_7_g2_a0 eqa5' has been expanded (cost =
1):
MODULE_7_g2_a0 eqa5 <= ((not licznik_10 and not licznik_9 and not licznik_8
and not licznik_7 and not licznik_6 and not licznik_5));
Note: Virtual equation for 'MODULE_7_g2_a0 eqa4' has been expanded (cost =
1):
MODULE_7_g2_a0 eqa4 <= ((not licznik_10 and not licznik_9 and not licznik_8
and not licznik_7 and not licznik_6 and not licznik_5 and not licznik_4));
Note: Virtual equation for 'MODULE_7_g2_a0 eqa3' has been expanded (cost =
1):
MODULE_7_g2_a0 eqa3 <= ((not licznik_10 and not licznik_9 and not licznik_8
and not licznik_7 and not licznik_6 and not licznik_5 and not licznik_4 and
not licznik_3));
Note: Virtual equation for 'MODULE_7_g2_a0 eqa2' has been expanded (cost =
1):
MODULE_7_g2_a0 eqa2 <= ((not clk_4 and not licznik_10 and not licznik_9 and
not licznik_8 and not licznik_7 and not licznik_6 and not licznik_5 and not
licznik_4 and not licznik_3));
Note: Virtual equation for 'MODULE_8_g2_a0 eqa10' has been expanded (cost
= 0):
MODULE_8_g2_a0 eqa10 <= (not licznik_10);
Note: Virtual equation for 'MODULE_8_g2_a0 eqa9' has been expanded (cost =
1):
MODULE_8_g2_a0 eqa9 <= ((not licznik_10 and not licznik_9));
Note: Virtual equation for 'MODULE_8_g2_a0 eqa8' has been expanded (cost =
1):
MODULE_8_g2_a0 eqa8 <= ((not licznik_10 and not licznik_9 and not
licznik_8));
Note: Virtual equation for 'MODULE_8_g2_a0 eqa7' has been expanded (cost =
1):
MODULE_8_g2_a0 eqa7 <= ((not licznik_10 and not licznik_9 and not licznik_8
and not licznik_7));
Note: Virtual equation for 'MODULE_8_g2_a0 eqa6' has been expanded (cost =
1):
MODULE_8_g2_a0 eqa6 <= ((not licznik_10 and not licznik_9 and not licznik_8
and not licznik_7 and not licznik_6));
Note: Virtual equation for 'MODULE_8_g2_a0 eqa5' has been expanded (cost =
1):
MODULE_8_g2_a0 eqa5 <= ((not licznik_10 and not licznik_9 and not licznik_8
and not licznik_7 and not licznik_6 and not licznik_5));
Note: Virtual equation for 'MODULE_8_g2_a0 eqa4' has been expanded (cost =
1):
MODULE_8_g2_a0 eqa4 <= ((not licznik_10 and not licznik_9 and not licznik_8
and not licznik_7 and not licznik_6 and not licznik_5 and not licznik_4));
Note: Virtual equation for 'MODULE_8_g2_a0 eqa3' has been expanded (cost =
1):
MODULE_8_g2_a0 eqa3 <= ((not licznik_10 and not licznik_9 and not licznik_8
and not licznik_7 and not licznik_6 and not licznik_5 and not licznik_4 and
not licznik_3));
Note: Virtual equation for 'MODULE_8_g2_a0 eqa2' has been expanded (cost =
1):
MODULE_8_g2_a0 eqa2 <= ((not clk_4 and not licznik_10 and not licznik_9 and
not licznik_8 and not licznik_7 and not licznik_6 and not licznik_5 and not
licznik_4 and not licznik_3));
Substituting virtuals - pass 2:
Note: Virtual equation for 'MODULE_1_g2_a0 eqa1' has been expanded (cost =
1):
MODULE_1_g2_a0 eqa1 <= ((not clk_4 and not licznik_9 and not licznik_8 and
not licznik_5 and not licznik_4 and not licznik_1 and licznik_10 and
licznik_7 and licznik_6 and licznik_3));
Note: Virtual equation for 'MODULE_6_g2_a0_g1_z1_s0_g1_u0 c1' has been
expanded (cost = 0):
MODULE_6_g2_a0_g1_z1_s0_g1_u0 c1 <= (licznik_0);
Note: Virtual equation for 'add_vi_ss_MODGEN_2_0' has been expanded (cost =
0):
add_vi_ss_MODGEN_2_0 <= (not licznik_0);
Note: Virtual equation for 'MODULE_7_g2_a0 eqa1' has been expanded (cost =
1):
MODULE_7_g2_a0 eqa1 <= ((not clk_4 and not licznik_10 and not licznik_9 and
not licznik_8 and not licznik_7 and not licznik_6 and not licznik_5 and not
licznik_4 and not licznik_3 and not licznik_1));
Note: Virtual equation for 'MODULE_8_g2_a0 eqa1' has been expanded (cost =
1):
MODULE_8_g2_a0 eqa1 <= ((not clk_4 and not licznik_10 and not licznik_9 and
not licznik_8 and not licznik_7 and not licznik_6 and not licznik_5 and not
licznik_4 and not licznik_3 and not licznik_1));
Note: Virtual equation for 'MODULE_2_g2_a0 eqa1' has been expanded (cost =
1):
MODULE_2_g2_a0 eqa1 <= ((not clk_4 and not licznik_10 and not licznik_9 and
not licznik_6 and not licznik_5 and not licznik_1 and licznik_8 and
licznik_7 and licznik_4 and licznik_3));
Note: Virtual equation for 'MODULE_4_g2_a0 eqa1' has been expanded (cost =
1):
MODULE_4_g2_a0 eqa1 <= ((not clk_4 and not licznik_10 and not licznik_9 and
not licznik_6 and not licznik_5 and not licznik_1 and licznik_8 and
licznik_7 and licznik_4 and licznik_3));
Note: Virtual equation for 'MODULE_3_g2_a0 eqa1' has been expanded (cost =
1):
MODULE_3_g2_a0 eqa1 <= ((not clk_4 and not licznik_10 and not licznik_7 and
not licznik_6 and not licznik_3 and not licznik_1 and licznik_9 and
licznik_8 and licznik_5 and licznik_4));
Note: Virtual equation for 'MODULE_5_g2_a0 eqa1' has been expanded (cost =
1):
MODULE_5_g2_a0 eqa1 <= ((not clk_4 and not licznik_10 and not licznik_7 and
not licznik_6 and not licznik_3 and not licznik_1 and licznik_9 and
licznik_8 and licznik_5 and licznik_4));
Substituting virtuals - pass 3:
Note: Virtual equation for 'cmp_vv_ss_MODGEN_1' has been expanded (cost =
121):
cmp_vv_ss_MODGEN_1 <= ((not clk_4 and not licznik_9 and not licznik_8 and
not licznik_5 and not licznik_4 and not licznik_1 and not licznik_0 and
licznik_10 and licznik_7 and licznik_6 and licznik_3));
Note: Virtual equation for 'MODULE_6_g2_a0_g1_z1_s0_g1_u0 c2' has been
expanded (cost = 3):
MODULE_6_g2_a0_g1_z1_s0_g1_u0 c2 <= ((licznik_1 and licznik_0));
Note: Virtual equation for 'add_vi_ss_MODGEN_2_1' has been expanded (cost =
22):
add_vi_ss_MODGEN_2_1 <= ((not licznik_0 and licznik_1)
OR (not licznik_1 and licznik_0));
Note: Virtual equation for 'cmp_vv_ss_MODGEN_3' has been expanded (cost =
1):
cmp_vv_ss_MODGEN_3 <= ((not clk_4 and not licznik_10 and not licznik_9 and
not licznik_8 and not licznik_7 and not licznik_6 and not licznik_5 and not
licznik_4 and not licznik_3 and not licznik_1 and not licznik_0));
Note: Virtual equation for 'cmp_vv_ss_MODGEN_4' has been expanded (cost =
1):
cmp_vv_ss_MODGEN_4 <= ((not clk_4 and not licznik_10 and not licznik_9 and
not licznik_8 and not licznik_7 and not licznik_6 and not licznik_5 and not
licznik_4 and not licznik_3 and not licznik_1 and licznik_0));
Note: Virtual equation for 'cmp_vv_ss_MODGEN_5' has been expanded (cost =
1):
cmp_vv_ss_MODGEN_5 <= ((not clk_4 and not licznik_10 and not licznik_9 and
not licznik_6 and not licznik_5 and not licznik_1 and not licznik_0 and
licznik_8 and licznik_7 and licznik_4 and licznik_3));
Note: Virtual equation for 'cmp_vv_ss_MODGEN_6' has been expanded (cost =
1):
cmp_vv_ss_MODGEN_6 <= ((not clk_4 and not licznik_10 and not licznik_9 and
not licznik_6 and not licznik_5 and not licznik_1 and licznik_8 and
licznik_7 and licznik_4 and licznik_3 and licznik_0));
Note: Virtual equation for 'cmp_vv_ss_MODGEN_7' has been expanded (cost =
1):
cmp_vv_ss_MODGEN_7 <= ((not clk_4 and not licznik_10 and not licznik_7 and
not licznik_6 and not licznik_3 and not licznik_1 and not licznik_0 and
licznik_9 and licznik_8 and licznik_5 and licznik_4));
Note: Virtual equation for 'cmp_vv_ss_MODGEN_8' has been expanded (cost =
1):
cmp_vv_ss_MODGEN_8 <= ((not clk_4 and not licznik_10 and not licznik_7 and
not licznik_6 and not licznik_3 and not licznik_1 and licznik_9 and
licznik_8 and licznik_5 and licznik_4 and licznik_0));
Substituting virtuals - pass 4:
Note: Virtual equation for 'MODULE_6_g2_a0_g1_z1_s0_g1_u0 c3' has been
expanded (cost = 3):
MODULE_6_g2_a0_g1_z1_s0_g1_u0 c3 <= ((clk_4 and licznik_1 and licznik_0));
Note: Virtual equation for 'add_vi_ss_MODGEN_2_2' has been expanded (cost =
33):
add_vi_ss_MODGEN_2_2 <= ((not licznik_1 and clk_4)
OR (not licznik_0 and clk_4)
OR (not clk_4 and licznik_1 and licznik_0));
Substituting virtuals - pass 5:
Note: Virtual equation for 'MODULE_6_g2_a0_g1_z1_s0_g1_u0 c4' has been
expanded (cost = 3):
MODULE_6_g2_a0_g1_z1_s0_g1_u0 c4 <= ((clk_4 and licznik_3 and licznik_1 and
licznik_0));
Note: Virtual equation for 'add_vi_ss_MODGEN_2_3' has been expanded (cost =
44):
add_vi_ss_MODGEN_2_3 <= ((not clk_4 and licznik_3)
OR (not licznik_1 and licznik_3)
OR (not licznik_0 and licznik_3)
OR (not licznik_3 and clk_4 and licznik_1 and licznik_0));
Substituting virtuals - pass 6:
Note: Virtual equation for 'MODULE_6_g2_a0_g1_z1_s0_g1_u0 c5' has been
expanded (cost = 3):
MODULE_6_g2_a0_g1_z1_s0_g1_u0 c5 <= ((clk_4 and licznik_4 and licznik_3 and
licznik_1 and licznik_0));
Note: Virtual equation for 'add_vi_ss_MODGEN_2_4' has been expanded (cost =
55):
add_vi_ss_MODGEN_2_4 <= ((not clk_4 and licznik_4)
OR (not licznik_3 and licznik_4)
OR (not licznik_1 and licznik_4)
OR (not licznik_0 and licznik_4)
OR (not licznik_4 and clk_4 and licznik_3 and licznik_1 and licznik_0));
Substituting virtuals - pass 7:
Note: Virtual equation for 'MODULE_6_g2_a0_g1_z1_s0_g1_u0 c6' has been
expanded (cost = 3):
MODULE_6_g2_a0_g1_z1_s0_g1_u0 c6 <= ((clk_4 and licznik_5 and licznik_4 and
licznik_3 and licznik_1 and licznik_0));
Note: Virtual equation for 'add_vi_ss_MODGEN_2_5' has been expanded (cost =
66):
add_vi_ss_MODGEN_2_5 <= ((not clk_4 and licznik_5)
OR (not licznik_4 and licznik_5)
OR (not licznik_3 and licznik_5)
OR (not licznik_1 and licznik_5)
OR (not licznik_0 and licznik_5)
OR (not licznik_5 and clk_4 and licznik_4 and licznik_3 and licznik_1 and
licznik_0));
Substituting virtuals - pass 8:
Note: Virtual equation for 'MODULE_6_g2_a0_g1_z1_s0_g1_u0 c7' has been
expanded (cost = 3):
MODULE_6_g2_a0_g1_z1_s0_g1_u0 c7 <= ((clk_4 and licznik_6 and licznik_5 and
licznik_4 and licznik_3 and licznik_1 and licznik_0));
Note: Virtual equation for 'add_vi_ss_MODGEN_2_6' has been expanded (cost =
77):
add_vi_ss_MODGEN_2_6 <= ((not clk_4 and licznik_6)
OR (not licznik_5 and licznik_6)
OR (not licznik_4 and licznik_6)
OR (not licznik_3 and licznik_6)
OR (not licznik_1 and licznik_6)
OR (not licznik_0 and licznik_6)
OR (not licznik_6 and clk_4 and licznik_5 and licznik_4 and licznik_3 and
licznik_1 and licznik_0));
Substituting virtuals - pass 9:
Note: Virtual equation for 'MODULE_6_g2_a0_g1_z1_s0_g1_u0 c8' has been
expanded (cost = 3):
MODULE_6_g2_a0_g1_z1_s0_g1_u0 c8 <= ((clk_4 and licznik_7 and licznik_6 and
licznik_5 and licznik_4 and licznik_3 and licznik_1 and licznik_0));
Note: Virtual equation for 'add_vi_ss_MODGEN_2_7' has been expanded (cost =
88):
add_vi_ss_MODGEN_2_7 <= ((not clk_4 and licznik_7)
OR (not licznik_6 and licznik_7)
OR (not licznik_5 and licznik_7)
OR (not licznik_4 and licznik_7)
OR (not licznik_3 and licznik_7)
OR (not licznik_1 and licznik_7)
OR (not licznik_0 and licznik_7)
OR (not licznik_7 and clk_4 and licznik_6 and licznik_5 and licznik_4 and
licznik_3 and licznik_1 and licznik_0));
Substituting virtuals - pass 10:
Note: Virtual equation for 'MODULE_6_g2_a0_g1_z1_s0_g1_u0 c9' has been
expanded (cost = 3):
MODULE_6_g2_a0_g1_z1_s0_g1_u0 c9 <= ((clk_4 and licznik_8 and licznik_7 and
licznik_6 and licznik_5 and licznik_4 and licznik_3 and licznik_1 and
licznik_0));
Note: Virtual equation for 'add_vi_ss_MODGEN_2_8' has been expanded (cost =
99):
add_vi_ss_MODGEN_2_8 <= ((not clk_4 and licznik_8)
OR (not licznik_7 and licznik_8)
OR (not licznik_6 and licznik_8)
OR (not licznik_5 and licznik_8)
OR (not licznik_4 and licznik_8)
OR (not licznik_3 and licznik_8)
OR (not licznik_1 and licznik_8)
OR (not licznik_0 and licznik_8)
OR (not licznik_8 and clk_4 and licznik_7 and licznik_6 and licznik_5 and
licznik_4 and licznik_3 and licznik_1 and licznik_0));
Substituting virtuals - pass 11:
Note: Virtual equation for 'MODULE_6_g2_a0_g1_z1_s0_g1_u0 c10' has been
expanded (cost = 2):
MODULE_6_g2_a0_g1_z1_s0_g1_u0 c10 <= ((clk_4 and licznik_9 and licznik_8
and licznik_7 and licznik_6 and licznik_5 and licznik_4 and licznik_3 and
licznik_1 and licznik_0));
Note: Virtual equation for 'add_vi_ss_MODGEN_2_9' has been expanded (cost =
110):
add_vi_ss_MODGEN_2_9 <= ((not clk_4 and licznik_9)
OR (not licznik_8 and licznik_9)
OR (not licznik_7 and licznik_9)
OR (not licznik_6 and licznik_9)
OR (not licznik_5 and licznik_9)
OR (not licznik_4 and licznik_9)
OR (not licznik_3 and licznik_9)
OR (not licznik_1 and licznik_9)
OR (not licznik_0 and licznik_9)
OR (not licznik_9 and clk_4 and licznik_8 and licznik_7 and licznik_6 and
licznik_5 and licznik_4 and licznik_3 and licznik_1 and licznik_0));
Substituting virtuals - pass 12:
Note: Virtual equation for 'add_vi_ss_MODGEN_2_10' has been expanded (cost
= 121):
add_vi_ss_MODGEN_2_10 <= ((not licznik_10 and clk_4 and licznik_9 and
licznik_8 and licznik_7 and licznik_6 and licznik_5 and licznik_4 and
licznik_3 and licznik_1 and licznik_0)
OR (not clk_4 and licznik_10)
OR (not licznik_9 and licznik_10)
OR (not licznik_8 and licznik_10)
OR (not licznik_7 and licznik_10)
OR (not licznik_6 and licznik_10)
OR (not licznik_5 and licznik_10)
OR (not licznik_4 and licznik_10)
OR (not licznik_3 and licznik_10)
OR (not licznik_1 and licznik_10)
OR (not licznik_0 and licznik_10));
Substituting virtuals - pass 13:
----------------------------------------------------------
Circuit simplification results:
Expanded 99 signals.
Turned 0 signals into soft nodes.
Maximum expansion cost was set at 10.
----------------------------------------------------------
Created 273 PLD nodes.
Note: Removed unneeded node 'cmp_vv_ss_MODGEN_1'.
Note: Removed unneeded node 'add_vi_ss_MODGEN_2_10'.
Note: Removed unneeded node 'add_vi_ss_MODGEN_2_9'.
Note: Removed unneeded node 'add_vi_ss_MODGEN_2_8'.
Note: Removed unneeded node 'add_vi_ss_MODGEN_2_7'.
Note: Removed unneeded node 'add_vi_ss_MODGEN_2_6'.
Note: Removed unneeded node 'add_vi_ss_MODGEN_2_5'.
Note: Removed unneeded node 'add_vi_ss_MODGEN_2_4'.
Note: Removed unneeded node 'add_vi_ss_MODGEN_2_3'.
Note: Removed unneeded node 'add_vi_ss_MODGEN_2_2'.
Note: Removed unneeded node 'add_vi_ss_MODGEN_2_1'.
Note: Removed unneeded node 'add_vi_ss_MODGEN_2_0'.
Note: Removed unneeded node 'licznik_9R'.
Note: Removed unneeded node 'licznik_9S'.
Note: Removed unneeded node 'licznik_8R'.
Note: Removed unneeded node 'licznik_8S'.
Note: Removed unneeded node 'licznik_7R'.
Note: Removed unneeded node 'licznik_7S'.
Note: Removed unneeded node 'licznik_6R'.
Note: Removed unneeded node 'licznik_6S'.
Note: Removed unneeded node 'licznik_5R'.
Note: Removed unneeded node 'licznik_5S'.
Note: Removed unneeded node 'licznik_4R'.
Note: Removed unneeded node 'licznik_4S'.
Note: Removed unneeded node 'licznik_3R'.
Note: Removed unneeded node 'licznik_3S'.
Note: Removed unneeded node 'licznik_2R'.
Note: Removed unneeded node 'licznik_2S'.
Note: Removed unneeded node 'licznik_1R'.
Note: Removed unneeded node 'licznik_1S'.
Note: Removed unneeded node 'licznik_0R'.
Note: Removed unneeded node 'licznik_0S'.
Note: Removed unneeded node 'adstartR'.
Note: Removed unneeded node 'adstartS'.
Note: Removed unneeded node 'cmp_vv_ss_MODGEN_3'.
Note: Removed unneeded node 'cmp_vv_ss_MODGEN_4'.
Note: Removed unneeded node 's1R'.
Note: Removed unneeded node 's1S'.
Note: Removed unneeded node 'cmp_vv_ss_MODGEN_5'.
Note: Removed unneeded node 'cmp_vv_ss_MODGEN_6'.
Note: Removed unneeded node 's2R'.
Note: Removed unneeded node 's2S'.
Note: Removed unneeded node 'cmp_vv_ss_MODGEN_7'.
Note: Removed unneeded node 'cmp_vv_ss_MODGEN_8'.
Note: Removed unneeded node 's3R'.
Note: Removed unneeded node 's3S'.
Note: Removed unneeded node 'MODULE_1_g2_a0 eqa11'.
Note: Removed unneeded node 'MODULE_1_g2_a0 eqa10'.
Note: Removed unneeded node 'MODIN1_10'.
Note: Removed unneeded node 'MODULE_1_g2_a0 eqa9'.
Note: Removed unneeded node 'MODIN1_9'.
Note: Removed unneeded node 'MODULE_1_g2_a0 eqa8'.
Note: Removed unneeded node 'MODIN1_8'.
Note: Removed unneeded node 'MODULE_1_g2_a0 eqa7'.
Note: Removed unneeded node 'MODIN1_7'.
Note: Removed unneeded node 'MODULE_1_g2_a0 eqa6'.
Note: Removed unneeded node 'MODIN1_6'.
Note: Removed unneeded node 'MODULE_1_g2_a0 eqa5'.
Note: Removed unneeded node 'MODIN1_5'.
Note: Removed unneeded node 'MODULE_1_g2_a0 eqa4'.
Note: Removed unneeded node 'MODIN1_4'.
Note: Removed unneeded node 'MODULE_1_g2_a0 eqa3'.
Note: Removed unneeded node 'MODIN1_3'.
Note: Removed unneeded node 'MODULE_1_g2_a0 eqa2'.
Note: Removed unneeded node 'MODIN1_2'.
Note: Removed unneeded node 'MODULE_1_g2_a0 eqa1'.
Note: Removed unneeded node 'MODIN1_1'.
Note: Removed unneeded node 'MODULE_1_g2_a0 eqa0'.
Note: Removed unneeded node 'MODIN1_0'.
Note: Removed unneeded node 'MODULE_2_g2_a0 eqa11'.
Note: Removed unneeded node 'MODULE_2_g2_a0 eqa10'.
Note: Removed unneeded node 'MODIN2_10'.
Note: Removed unneeded node 'MODULE_2_g2_a0 eqa9'.
Note: Removed unneeded node 'MODIN2_9'.
Note: Removed unneeded node 'MODULE_2_g2_a0 eqa8'.
Note: Removed unneeded node 'MODIN2_8'.
Note: Removed unneeded node 'MODULE_2_g2_a0 eqa7'.
Note: Removed unneeded node 'MODIN2_7'.
Note: Removed unneeded node 'MODULE_2_g2_a0 eqa6'.
Note: Removed unneeded node 'MODIN2_6'.
Note: Removed unneeded node 'MODULE_2_g2_a0 eqa5'.
Note: Removed unneeded node 'MODIN2_5'.
Note: Removed unneeded node 'MODULE_2_g2_a0 eqa4'.
Note: Removed unneeded node 'MODIN2_4'.
Note: Removed unneeded node 'MODULE_2_g2_a0 eqa3'.
Note: Removed unneeded node 'MODIN2_3'.
Note: Removed unneeded node 'MODULE_2_g2_a0 eqa2'.
Note: Removed unneeded node 'MODIN2_2'.
Note: Removed unneeded node 'MODULE_2_g2_a0 eqa1'.
Note: Removed unneeded node 'MODIN2_1'.
Note: Removed unneeded node 'MODULE_2_g2_a0 eqa0'.
Note: Removed unneeded node 'MODIN2_0'.
Note: Removed unneeded node 'MODULE_3_g2_a0 eqa11'.
Note: Removed unneeded node 'MODULE_3_g2_a0 eqa10'.
Note: Removed unneeded node 'MODIN3_10'.
Note: Removed unneeded node 'MODULE_3_g2_a0 eqa9'.
Note: Removed unneeded node 'MODIN3_9'.
Note: Removed unneeded node 'MODULE_3_g2_a0 eqa8'.
Note: Removed unneeded node 'MODIN3_8'.
Note: Removed unneeded node 'MODULE_3_g2_a0 eqa7'.
Note: Removed unneeded node 'MODIN3_7'.
Note: Removed unneeded node 'MODULE_3_g2_a0 eqa6'.
Note: Removed unneeded node 'MODIN3_6'.
Note: Removed unneeded node 'MODULE_3_g2_a0 eqa5'.
Note: Removed unneeded node 'MODIN3_5'.
Note: Removed unneeded node 'MODULE_3_g2_a0 eqa4'.
Note: Removed unneeded node 'MODIN3_4'.
Note: Removed unneeded node 'MODULE_3_g2_a0 eqa3'.
Note: Removed unneeded node 'MODIN3_3'.
Note: Removed unneeded node 'MODULE_3_g2_a0 eqa2'.
Note: Removed unneeded node 'MODIN3_2'.
Note: Removed unneeded node 'MODULE_3_g2_a0 eqa1'.
Note: Removed unneeded node 'MODIN3_1'.
Note: Removed unneeded node 'MODULE_3_g2_a0 eqa0'.
Note: Removed unneeded node 'MODIN3_0'.
Note: Removed unneeded node 'MODULE_4_g2_a0 eqa11'.
Note: Removed unneeded node 'MODULE_4_g2_a0 eqa10'.
Note: Removed unneeded node 'MODIN4_10'.
Note: Removed unneeded node 'MODULE_4_g2_a0 eqa9'.
Note: Removed unneeded node 'MODIN4_9'.
Note: Removed unneeded node 'MODULE_4_g2_a0 eqa8'.
Note: Removed unneeded node 'MODIN4_8'.
Note: Removed unneeded node 'MODULE_4_g2_a0 eqa7'.
Note: Removed unneeded node 'MODIN4_7'.
Note: Removed unneeded node 'MODULE_4_g2_a0 eqa6'.
Note: Removed unneeded node 'MODIN4_6'.
Note: Removed unneeded node 'MODULE_4_g2_a0 eqa5'.
Note: Removed unneeded node 'MODIN4_5'.
Note: Removed unneeded node 'MODULE_4_g2_a0 eqa4'.
Note: Removed unneeded node 'MODIN4_4'.
Note: Removed unneeded node 'MODULE_4_g2_a0 eqa3'.
Note: Removed unneeded node 'MODIN4_3'.
Note: Removed unneeded node 'MODULE_4_g2_a0 eqa2'.
Note: Removed unneeded node 'MODIN4_2'.
Note: Removed unneeded node 'MODULE_4_g2_a0 eqa1'.
Note: Removed unneeded node 'MODIN4_1'.
Note: Removed unneeded node 'MODULE_4_g2_a0 eqa0'.
Note: Removed unneeded node 'MODIN4_0'.
Note: Removed unneeded node 'MODULE_5_g2_a0 eqa11'.
Note: Removed unneeded node 'MODULE_5_g2_a0 eqa10'.
Note: Removed unneeded node 'MODIN5_10'.
Note: Removed unneeded node 'MODULE_5_g2_a0 eqa9'.
Note: Removed unneeded node 'MODIN5_9'.
Note: Removed unneeded node 'MODULE_5_g2_a0 eqa8'.
Note: Removed unneeded node 'MODIN5_8'.
Note: Removed unneeded node 'MODULE_5_g2_a0 eqa7'.
Note: Removed unneeded node 'MODIN5_7'.
Note: Removed unneeded node 'MODULE_5_g2_a0 eqa6'.
Note: Removed unneeded node 'MODIN5_6'.
Note: Removed unneeded node 'MODULE_5_g2_a0 eqa5'.
Note: Removed unneeded node 'MODIN5_5'.
Note: Removed unneeded node 'MODULE_5_g2_a0 eqa4'.
Note: Removed unneeded node 'MODIN5_4'.
Note: Removed unneeded node 'MODULE_5_g2_a0 eqa3'.
Note: Removed unneeded node 'MODIN5_3'.
Note: Removed unneeded node 'MODULE_5_g2_a0 eqa2'.
Note: Removed unneeded node 'MODIN5_2'.
Note: Removed unneeded node 'MODULE_5_g2_a0 eqa1'.
Note: Removed unneeded node 'MODIN5_1'.
Note: Removed unneeded node 'MODULE_5_g2_a0 eqa0'.
Note: Removed unneeded node 'MODIN5_0'.
Note: Removed unneeded node 'MODULE_6_g2_a0 s10'.
Note: Removed unneeded node 'MODULE_6_g2_a0 s9'.
Note: Removed unneeded node 'MODULE_6_g2_a0 s8'.
Note: Removed unneeded node 'MODULE_6_g2_a0 s7'.
Note: Removed unneeded node 'MODULE_6_g2_a0 s6'.
Note: Removed unneeded node 'MODULE_6_g2_a0 s5'.
Note: Removed unneeded node 'MODULE_6_g2_a0 s4'.
Note: Removed unneeded node 'MODULE_6_g2_a0 s3'.
Note: Removed unneeded node 'MODULE_6_g2_a0 s2'.
Note: Removed unneeded node 'MODULE_6_g2_a0 s1'.
Note: Removed unneeded node 'MODULE_6_g2_a0 s0'.
Note: Removed unneeded node 'MODULE_6_g2_a0_g1_z1_s0_g1_u0 c10'.
Note: Removed unneeded node 'MODIN6_9'.
Note: Removed unneeded node 'MODULE_6_g2_a0_g1_z1_s0_g1_u0 c9'.
Note: Removed unneeded node 'MODIN6_10'.
Note: Removed unneeded node 'MODIN6_8'.
Note: Removed unneeded node 'MODULE_6_g2_a0_g1_z1_s0_g1_u0 c8'.
Note: Removed unneeded node 'MODIN6_7'.
Note: Removed unneeded node 'MODULE_6_g2_a0_g1_z1_s0_g1_u0 c7'.
Note: Removed unneeded node 'MODIN6_6'.
Note: Removed unneeded node 'MODULE_6_g2_a0_g1_z1_s0_g1_u0 c6'.
Note: Removed unneeded node 'MODIN6_5'.
Note: Removed unneeded node 'MODULE_6_g2_a0_g1_z1_s0_g1_u0 c5'.
Note: Removed unneeded node 'MODIN6_4'.
Note: Removed unneeded node 'MODULE_6_g2_a0_g1_z1_s0_g1_u0 c4'.
Note: Removed unneeded node 'MODIN6_3'.
Note: Removed unneeded node 'MODULE_6_g2_a0_g1_z1_s0_g1_u0 c3'.
Note: Removed unneeded node 'MODIN6_2'.
Note: Removed unneeded node 'MODULE_6_g2_a0_g1_z1_s0_g1_u0 c2'.
Note: Removed unneeded node 'MODIN6_1'.
Note: Removed unneeded node 'MODULE_6_g2_a0_g1_z1_s0_g1_u0 c1'.
Note: Removed unneeded node 'MODIN6_0'.
Note: Removed unneeded node 'MODULE_6_g2_a0_g1_z1_s0_g1_u0 c0'.
Note: Removed unneeded node 'MODULE_7_g2_a0 eqa10'.
Note: Removed unneeded node 'MODIN7_10'.
Note: Removed unneeded node 'MODULE_7_g2_a0 eqa9'.
Note: Removed unneeded node 'MODIN7_9'.
Note: Removed unneeded node 'MODULE_7_g2_a0 eqa8'.
Note: Removed unneeded node 'MODIN7_8'.
Note: Removed unneeded node 'MODULE_7_g2_a0 eqa7'.
Note: Removed unneeded node 'MODIN7_7'.
Note: Removed unneeded node 'MODULE_7_g2_a0 eqa6'.
Note: Removed unneeded node 'MODIN7_6'.
Note: Removed unneeded node 'MODULE_7_g2_a0 eqa5'.
Note: Removed unneeded node 'MODIN7_5'.
Note: Removed unneeded node 'MODULE_7_g2_a0 eqa4'.
Note: Removed unneeded node 'MODIN7_4'.
Note: Removed unneeded node 'MODULE_7_g2_a0 eqa3'.
Note: Removed unneeded node 'MODIN7_3'.
Note: Removed unneeded node 'MODULE_7_g2_a0 eqa2'.
Note: Removed unneeded node 'MODIN7_2'.
Note: Removed unneeded node 'MODULE_7_g2_a0 eqa1'.
Note: Removed unneeded node 'MODIN7_1'.
Note: Removed unneeded node 'MODULE_7_g2_a0 eqa0'.
Note: Removed unneeded node 'MODIN7_0'.
Note: Removed unneeded node 'MODULE_8_g2_a0 eqa10'.
Note: Removed unneeded node 'MODIN8_10'.
Note: Removed unneeded node 'MODULE_8_g2_a0 eqa9'.
Note: Removed unneeded node 'MODIN8_9'.
Note: Removed unneeded node 'MODULE_8_g2_a0 eqa8'.
Note: Removed unneeded node 'MODIN8_8'.
Note: Removed unneeded node 'MODULE_8_g2_a0 eqa7'.
Note: Removed unneeded node 'MODIN8_7'.
Note: Removed unneeded node 'MODULE_8_g2_a0 eqa6'.
Note: Removed unneeded node 'MODIN8_6'.
Note: Removed unneeded node 'MODULE_8_g2_a0 eqa5'.
Note: Removed unneeded node 'MODIN8_5'.
Note: Removed unneeded node 'MODULE_8_g2_a0 eqa4'.
Note: Removed unneeded node 'MODIN8_4'.
Note: Removed unneeded node 'MODULE_8_g2_a0 eqa3'.
Note: Removed unneeded node 'MODIN8_3'.
Note: Removed unneeded node 'MODULE_8_g2_a0 eqa2'.
Note: Removed unneeded node 'MODIN8_2'.
Note: Removed unneeded node 'MODULE_8_g2_a0 eqa1'.
Note: Removed unneeded node 'MODIN8_1'.
Note: Removed unneeded node 'MODULE_8_g2_a0 eqa0'.
Note: Removed unneeded node 'MODIN8_0'.
Note: Removed unneeded node 'licznik_2'.
Note: Removed unneeded node 'licznik_10R'.
Note: Removed unneeded node 'licznik_10S'.
C:\warp\bin\topld.exe: No errors.
----------------------------------------------------------------------------
PLD Optimizer Software: DSGNOPT.EXE 19 JUN1998 [v4.02 ] 4 IR x96
DESIGN HEADER INFORMATION (20:37:38)
Input File(s): gal0.pla
Device : c371i
Package : CY7C371I-66AC
ReportFile : gal0.rpt
Program Controls:
None.
Signal Requests:
GROUP RESERVE_PINS 33 21 13 1
GROUP DT-OPT ALL
GROUP FAST_SLEW ALL
Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software: DSGNOPT.EXE 19 JUN1998 [v4.02 ] 4 IR x96
OPTIMIZATION OPTIONS (20:37:38)
Messages:
Information: Process virtual 'licznik_0D' ... expanded.
Information: Process virtual 'licznik_1D' ... expanded.
Information: Process virtual 'licznik_2D' ... expanded.
Information: Process virtual 'licznik_3D' ... expanded.
Information: Process virtual 'licznik_4D' ... expanded.
Information: Process virtual 'licznik_5D' ... expanded.
Information: Process virtual 'licznik_6D' ... expanded.
Information: Process virtual 'licznik_7D' ... expanded.
Information: Process virtual 'licznik_8D' ... expanded.
Information: Process virtual 'licznik_9D' ... expanded.
Information: Process virtual 'licznik_10D' ... expanded.
Information: Process virtual 'adstartD' ... expanded.
Information: Process virtual 'licznik_0' ... converted to NODE.
Information: Process virtual 'licznik_1' ... converted to NODE.
Information: Process virtual 'licznik_3' ... converted to NODE.
Information: Process virtual 'licznik_4' ... converted to NODE.
Information: Process virtual 'licznik_5' ... converted to NODE.
Information: Process virtual 'licznik_6' ... converted to NODE.
Information: Process virtual 'licznik_7' ... converted to NODE.
Information: Process virtual 'licznik_8' ... converted to NODE.
Information: Process virtual 'licznik_9' ... converted to NODE.
Information: Process virtual 'licznik_10' ... converted to NODE.
Information: Process virtual 's3D' ... expanded.
Information: Process virtual 's2D' ... expanded.
Information: Process virtual 's1D' ... expanded.
Information: Generating both D & T register equations for signal s1.D[42]
Information: Expanding XOR equation found on signal s1.T[42]
Information: Generating both D & T register equations for signal s3.D[3]
Information: Expanding XOR equation found on signal s3.T[3]
Information: Generating both D & T register equations for signal s2.D[18]
Information: Expanding XOR equation found on signal s2.T[18]
Information: Generating both D & T register equations for signal
adstart.D[19]
Information: Expanding XOR equation found on signal adstart.T[19]
Information: Generating both D & T register equations for signal
clk_4.D[24]
Information: Expanding XOR equation found on signal clk_4.T[24]
Information: Generating both D & T register equations for signal
licznik_0.D
Information: Expanding XOR equation found on signal licznik_0.T
Information: Generating both D & T register equations for signal
licznik_1.D
Information: Expanding XOR equation found on signal licznik_1.T
Information: Generating both D & T register equations for signal
licznik_3.D
Information: Expanding XOR equation found on signal licznik_3.T
Information: Generating both D & T register equations for signal
licznik_4.D
Information: Expanding XOR equation found on signal licznik_4.T
Information: Generating both D & T register equations for signal
licznik_5.D
Information: Expanding XOR equation found on signal licznik_5.T
Information: Generating both D & T register equations for signal
licznik_6.D
Information: Expanding XOR equation found on signal licznik_6.T
Information: Generating both D & T register equations for signal
licznik_7.D
Information: Expanding XOR equation found on signal licznik_7.T
Information: Generating both D & T register equations for signal
licznik_8.D
Information: Expanding XOR equation found on signal licznik_8.T
Information: Generating both D & T register equations for signal
licznik_9.D
Information: Expanding XOR equation found on signal licznik_9.T
Information: Generating both D & T register equations for signal
licznik_10.D
Information: Expanding XOR equation found on signal licznik_10.T
Information: Optimizing logic without changing polarity for signals:
s1.T s3.T s2.T clk_4.T licznik_0.T licznik_1.T licznik_3.T
licznik_4.T licznik_5.T licznik_6.T licznik_7.T licznik_8.T
licznik_9.T licznik_10.T
Information: Optimizing logic using best output polarity for signals:
adstart.D clk_4.D licznik_0.D licznik_1.D licznik_3.D licznik_4.D
licznik_5.D licznik_6.D licznik_7.D licznik_8.D licznik_9.D
licznik_10.D
Information: Selected logic optimization OFF for signals:
s1.D s1.AR s1.C s3.D s3.AR s3.C s2.D s2.AR s2.C adstart.T
adstart.AR
adstart.C clk_4.AR clk_4.C licznik_0.AR licznik_0.C licznik_1.AR
licznik_1.C licznik_3.AR licznik_3.C licznik_4.AR licznik_4.C
licznik_5.AR licznik_5.C licznik_6.AR licznik_6.C licznik_7.AR
licznik_7.C licznik_8.AR licznik_8.C licznik_9.AR licznik_9.C
licznik_10.AR licznik_10.C
Summary:
Error Count = 0 Warning Count = 0
Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software: MINOPT.EXE 11 NOV97 [v4.02 ] 4 IR x90
LOGIC MINIMIZATION ()
Messages:
Summary:
Error Count = 0 Warning Count = 0
Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software: DSGNOPT.EXE 19 JUN1998 [v4.02 ] 4 IR x96
OPTIMIZATION OPTIONS (20:37:39)
Messages:
Information: Optimizing Banked Preset/Reset requirements.
Information: Selecting T register equation as minimal for signal licznik_1
Information: Selecting T register equation as minimal for signal licznik_4
Information: Selecting T register equation as minimal for signal licznik_5
Information: Selecting T register equation as minimal for signal licznik_8
Information: Selecting T register equation as minimal for signal licznik_9
Information: Selecting T register equation as minimal for signal
licznik_10
Information: Selecting T register equation as minimal for signal clk_4
Information: Selecting D register equation as minimal for signal s2
Information: Selecting D register equation as minimal for signal s3
Information: Selecting D register equation as minimal for signal s1
Information: Inverting Preset/Reset & output logic polarity for licznik_0.
Information: Selecting D register equation as minimal for signal licznik_0
Information: Inverting Preset/Reset & output logic polarity for licznik_3.
Information: Selecting T register equation as minimal for signal licznik_3
Information: Inverting Preset/Reset & output logic polarity for licznik_6.
Information: Selecting T register equation as minimal for signal licznik_6
Information: Inverting Preset/Reset & output logic polarity for licznik_7.
Information: Selecting T register equation as minimal for signal licznik_7
Information: Inverting Preset/Reset & output logic polarity for adstart.
Information: Selecting T register equation as minimal for signal adstart
Information: Optimizing logic without changing polarity for signals:
licznik_10.T licznik_7.T licznik_6.T licznik_3.T licznik_0.D
Information: Selected logic optimization OFF for signals:
s1.D s1.AP s1.AR s1.C s3.D s3.AP s3.AR s3.C s2.D s2.AP s2.AR s2.C
adstart.T adstart.AP adstart.AR adstart.C clk_4.T clk_4.AP clk_4.AR
clk_4.C licznik_10.AP licznik_10.AR licznik_10.C licznik_9.T
licznik_9.AP licznik_9.AR licznik_9.C licznik_8.T licznik_8.AP
licznik_8.AR licznik_8.C licznik_7.AP licznik_7.AR licznik_7.C
licznik_6.AP licznik_6.AR licznik_6.C licznik_5.T licznik_5.AP
licznik_5.AR licznik_5.C licznik_4.T licznik_4.AP licznik_4.AR
licznik_4.C licznik_3.AP licznik_3.AR licznik_3.C licznik_1.T
licznik_1.AP licznik_1.AR licznik_1.C licznik_0.AP licznik_0.AR
licznik_0.C
Summary:
Error Count = 0 Warning Count = 0
Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software: MINOPT.EXE 11 NOV97 [v4.02 ] 4 IR x90
LOGIC MINIMIZATION ()
Messages:
Summary:
Error Count = 0 Warning Count = 0
Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software: DSGNOPT.EXE 19 JUN1998 [v4.02 ] 4 IR x96
OPTIMIZATION OPTIONS (20:37:40)
Messages:
Summary:
Error Count = 0 Warning Count = 0
Completed Successfully
----------------------------------------------------------------------------
PLD Compiler Software: C37XFIT.EXE 19 JUN1998 [v4.02 ] 4 IR x96
DESIGN EQUATIONS (20:37:41)
s1.D =
clk4.Q * licznik10.Q * licznik9.Q * licznik8.Q *
licznik7.Q * licznik6.Q * licznik5.Q * licznik4.Q *
licznik3.Q * licznik1.Q
s1.AP =
GND
s1.AR =
/reset_n
s1.C =
clk
s3.D =
clk4.Q * licznik10.Q * licznik_9.Q * licznik_8.Q *
licznik7.Q * licznik6.Q * licznik_5.Q * licznik_4.Q *
licznik3.Q * licznik1.Q
s3.AP =
GND
s3.AR =
/reset_n
s3.C =
clk
s2.D =
clk4.Q * licznik10.Q * licznik9.Q * licznik_8.Q *
licznik_7.Q * licznik6.Q * licznik5.Q * licznik_4.Q *
licznik_3.Q * licznik1.Q
s2.AP =
GND
s2.AR =
/reset_n
s2.C =
clk
adstart.T =
s1.Q * /adstart.Q
adstart.AP =
GND
adstart.AR =
/reset_n
adstart.C =
clk
clk_4.T =
licznik_1.Q * licznik_0.Q
clk_4.AP =
GND
clk_4.AR =
/reset_n
clk_4.C =
clk
licznik_1.T =
licznik_0.Q
licznik_1.AP =
GND
licznik_1.AR =
/reset_n
licznik_1.C =
clk
licznik_4.T =
clk_4.Q * licznik_3.Q * licznik_1.Q * licznik_0.Q
licznik_4.AP =
GND
licznik_4.AR =
/reset_n
licznik_4.C =
clk
licznik_5.T =
clk_4.Q * licznik_4.Q * licznik_3.Q * licznik_1.Q * licznik_0.Q
licznik_5.AP =
GND
licznik_5.AR =
/reset_n
licznik_5.C =
clk
licznik_8.T =
clk_4.Q * licznik_7.Q * licznik_6.Q * licznik_5.Q * licznik_4.Q *
licznik_3.Q * licznik_1.Q * licznik_0.Q
licznik_8.AP =
GND
licznik_8.AR =
/reset_n
licznik_8.C =
clk
licznik_9.T =
clk_4.Q * licznik_8.Q * licznik_7.Q * licznik_6.Q * licznik_5.Q *
licznik_4.Q * licznik_3.Q * licznik_1.Q * licznik_0.Q
licznik_9.AP =
GND
licznik_9.AR =
/reset_n
licznik_9.C =
clk
licznik_0.D =
licznik_1.Q * licznik0.Q
+ licznik3.Q * licznik0.Q
+ licznik_4.Q * licznik0.Q
+ licznik_5.Q * licznik0.Q
+ licznik6.Q * licznik0.Q
+ licznik7.Q * licznik0.Q
+ licznik_8.Q * licznik0.Q
+ licznik_9.Q * licznik0.Q
+ licznik10.Q * licznik0.Q
+ clk_4.Q * licznik0.Q
licznik_0.AP =
GND
licznik_0.AR =
/reset_n
licznik_0.C =
clk
licznik_3.T =
clk4.Q * licznik_10.Q * licznik9.Q * licznik8.Q *
licznik_7.Q * licznik_6.Q * licznik5.Q * licznik4.Q *
licznik_3.Q * licznik1.Q * licznik0.Q
+ clk_4.Q * licznik_1.Q * licznik_0.Q
licznik_3.AP =
GND
licznik_3.AR =
/reset_n
licznik_3.C =
clk
licznik_6.T =
clk4.Q * licznik_10.Q * licznik9.Q * licznik8.Q *
licznik_7.Q * licznik_6.Q * licznik5.Q * licznik4.Q *
licznik_3.Q * licznik1.Q * licznik0.Q
+ clk_4.Q * licznik_5.Q * licznik_4.Q * licznik_3.Q * licznik_1.Q *
licznik_0.Q
licznik_6.AP =
GND
licznik_6.AR =
/reset_n
licznik_6.C =
clk
licznik_7.T =
clk4.Q * licznik_10.Q * licznik9.Q * licznik8.Q *
licznik_7.Q * licznik_6.Q * licznik5.Q * licznik4.Q *
licznik_3.Q * licznik1.Q * licznik0.Q
+ clk_4.Q * licznik_6.Q * licznik_5.Q * licznik_4.Q * licznik_3.Q *
licznik_1.Q * licznik_0.Q
licznik_7.AP =
GND
licznik_7.AR =
/reset_n
licznik_7.C =
clk
licznik_10.T =
clk4.Q * licznik_10.Q * licznik9.Q * licznik8.Q *
licznik_7.Q * licznik_6.Q * licznik5.Q * licznik4.Q *
licznik_3.Q * licznik1.Q * licznik0.Q
+ clk_4.Q * licznik_9.Q * licznik_8.Q * licznik_7.Q * licznik_6.Q *
licznik_5.Q * licznik_4.Q * licznik_3.Q * licznik_1.Q *
licznik_0.Q
licznik_10.AP =
GND
licznik_10.AR =
/reset_n
licznik_10.C =
clk
Completed Successfully
----------------------------------------------------------------------------
PLD Compiler Software: C37XFIT.EXE 19 JUN1998 [v4.02 ] 4 IR x96
DESIGN RULE CHECK (20:37:41)
Messages:
None.
Summary:
Error Count = 0 Warning Count = 0
Completed Successfully
----------------------------------------------------------------------------
PLD Compiler Software: C37XFIT.EXE 19 JUN1998 [v4.02 ] 4 IR x96
PARTITION LOGIC (20:37:41)
Messages:
Information: Checking design is strictly SYNCHRONOUS.
Information: Initializing Logic Block structures.
Information: Checking for duplicate NODE logic.
Information: Forming input seeds.
Information: Forming input seeds.
Information: Assigning fixed logic to Logic Blocks.
Information: Processing banked global preset, reset and output enable.
Information: Separating output logic set to GND/VCC.
Information: Validating Logic Block's with pre-placed signals.
Information: Assigning initializing equations to empty Logic Blocks.
Information: Separating output combinatorial logic.
Information: Separating disjoint output logic.
Information: Assigning floating outputs to Logic Blocks.
Information: Compacting Logic Block interconnect.
..............
Summary:
Error Count = 0 Warning Count = 0
Completed Successfully
----------------------------------------------------------------------------
PLD Compiler Software: C37XFIT.EXE 19 JUN1998 [v4.02 ] 4 IR x96
DESIGN SIGNAL PLACEMENT (20:37:42)
Messages:
Information: Fitting signals to Logic Block A.
Information: Assigning Signals to Macrocells.
Information: Assigning Product Terms to Allocator
Information: Fitting signals to Logic Block B.
Information: Assigning Signals to Macrocells.
Information: Improving Macrocell Assignment
................
Information: Assigning Product Terms to Allocator
Information: Combining 'licznik_4' definition with input pin 'Reserved4'.
Information: Combining 'licznik_5' definition with input pin 'Reserved3'.
Information: Routing signals to Logic Blocks.
Summary:
Error Count = 0 Warning Count = 0
Completed Successfully
----------------------------------------------------------------------------
PLD Compiler Software: C37XFIT.EXE 19 JUN1998 [v4.02 ] 4 IR x96
LOGIC BLOCK A PLACEMENT (20:37:42)
Messages:
__________________________________________________________________________
__
1111111111222222222233333333334444444444555555555566666666667777777777
0123456789012345678901234567890123456789012345678901234567890123456789012345
6789
__________________________________________________________________________
__
| 0 |UNUSED
++++++++++++++++............................................................
....
| 1 |UNUSED
......++++++++++++++++......................................................
....
| 2>|s1
..........X+++++++++++++++..................................................
....
| 3 |UNUSED
..............++++++++++++++++..............................................
....
| 4 |UNUSED
..................++++++++++++++++..........................................
....
| 5 |[i/p]
......................++++++++++++++++......................................
....
| 6 |UNUSED
..........................++++++++++++++++..................................
....
| 7>|s3
..............................X+++++++++++++++..............................
....
| 8 |UNUSED
..................................++++++++++++++++..........................
....
| 9 |UNUSED
......................................++++++++++++++++......................
....
|10 |UNUSED
..........................................++++++++++++++++..................
....
|11 |UNUSED
..............................................++++++++++++++++..............
....
|12 |UNUSED
..................................................++++++++++++++++..........
....
|13 |[i/p]
......................................................++++++++++++++++......
....
|14 |[i/p]
..........................................................++++++++++++++++..
....
|15 |UNUSED
................................................................++++++++++++
++++
__________________________________________________________________________
__
Total count of outputs placed = 2
Total count of unique Product Terms = 2
Total Product Terms to be assigned = 2
Max Product Terms used / available = 2 / 80 = 2.51 %
Control Signals for Logic Block A
---------------------------------
CLK pin 13 : clk
CLK pin 35 : <not used>
PRESET : GND
RESET : /reset_n
OE 0 : <not used>
OE 1 : <not used>
OE 2 : <not used>
OE 3 : <not used>
Logic Block A
__________________________________________
| |= >licznik_5.Q | |
| |= >licznik_6.Q | 40|* not used
| |= >clk_4.Q | |
| |= >licznik_7.Q | 41|* not used
| |> not used:49 | |
| |> not used:50 | 42|= s1
| |= >licznik_10.Q | |
| |= >licznik_1.Q | 43|* not used
| |= >licznik_4.Q | |
| |= >reset_n | 44|* not used
| |> not used:55 | |
| |> not used:56 | 1|= Reserved1
| |= >licznik_3.Q | |
| |= >licznik_9.Q | 2|* not used
| |> not used:59 | |
| |> not used:60 | 3|= s3
| |> not used:61 | |
| |> not used:62 | 8|* not used
| |= >licznik_8.Q | |
| |> not used:64 | 9|* not used
| |> not used:65 | |
| |> not used:66 | 10|* not used
| |> not used:67 | |
| |> not used:68 | 11|* not used
| |> not used:69 | |
| |> not used:70 | 12|* not used
| |> not used:71 | |
| |> not used:72 | 13|= Reserved2
| |> not used:73 | |
| |> not used:74 | 14|= reset_n
| |> not used:75 | |
| |> not used:76 | 15|* not used
| |> not used:77 | |
| |> not used:78 | |
| |> not used:79 | |
| |> not used:80 | |
__________________________________________
Information: Macrocell Utilization.
Description Used Max
____________________________________
| I/O Macrocells | 5 | 16 |
| PIM Input Connects | 11 | 36 |
____________________________________
16 / 52 = 30 %
----------------------------------------------------------------------------
PLD Compiler Software: C37XFIT.EXE 19 JUN1998 [v4.02 ] 4 IR x96
LOGIC BLOCK B PLACEMENT (20:37:42)
Messages:
__________________________________________________________________________
__
1111111111222222222233333333334444444444555555555566666666667777777777
0123456789012345678901234567890123456789012345678901234567890123456789012345
6789
__________________________________________________________________________
__
| 0>|s2
++X+++++++++++++............................................................
....
| 1>|adstart
......X+++++++++++++++......................................................
....
| 2 |(licznik_9)
..........X+++++++++++++++..................................................
....
| 3 |(licznik_5)Reserved3
..............X+++++++++++++++..............................................
....
| 4 |(licznik_1)
..................X+++++++++++++++..........................................
....
| 5 |(licznik_0)
......................XXXX+XXX+XXX++++......................................
....
| 6>|clk_4
..........................X+++++++++++++++..................................
....
| 7 |(licznik_3)
..............................X+++++++++++X+++..............................
....
| 8 |(licznik_6)
..................................X+++++++X+++++++..........................
....
| 9 |(licznik_7)
......................................X+++X+++++++++++......................
....
|10 |(licznik_10)
..........................................XX++++++++++++++..................
....
|11 |(licznik_4)Reserved4
..............................................X+++++++++++++++..............
....
|12 |(licznik_8)
..................................................X+++++++++++++++..........
....
|13 |UNUSED
......................................................++++++++++++++++......
....
|14 |UNUSED
..........................................................++++++++++++++++..
....
|15 |UNUSED
................................................................++++++++++++
++++
__________________________________________________________________________
__
Total count of outputs placed = 13
Total count of unique Product Terms = 23
Total Product Terms to be assigned = 26
Max Product Terms used / available = 23 / 80 = 28.76 %
Control Signals for Logic Block B
---------------------------------
CLK pin 13 : clk
CLK pin 35 : <not used>
PRESET : GND
RESET : /reset_n
OE 0 : <not used>
OE 1 : <not used>
OE 2 : <not used>
OE 3 : <not used>
Logic Block B
__________________________________________
| |= >licznik_5.Q | |
| |= >licznik_6.Q | 18|= s2
| |= >reset_n | |
| |= >licznik_7.Q | 19|= adstart
| |= >s1.Q | |
| |= >licznik_0.Q | 20|= (licznik_9)
| |= >licznik_10.Q | |
| |= >licznik_1.Q | 21|=
(licznik_5)Reserved3
| |= >licznik_4.Q | |
| |> not used:90 | 22|= (licznik_1)
| |> not used:91 | |
| |> not used:92 | 23|= (licznik_0)
| |= >licznik_3.Q | |
| |= >licznik_9.Q | 24|= clk_4
| |= >clk_4.Q | |
| |= >adstart.Q | 25|= (licznik_3)
| |> not used:97 | |
| |> not used:98 | 30|= (licznik_6)
| |= >licznik_8.Q | |
| |> not used:100 | 31|= (licznik_7)
| |> not used:101 | |
| |> not used:102 | 32|= (licznik_10)
| |> not used:103 | |
| |> not used:104 | 33|=
(licznik_4)Reserved4
| |> not used:105 | |
| |> not used:106 | 34|= (licznik_8)
| |> not used:107 | |
| |> not used:108 | 35|* not used
| |> not used:109 | |
| |> not used:110 | 36|* not used
| |> not used:111 | |
| |> not used:112 | 37|* not used
| |> not used:113 | |
| |> not used:114 | |
| |> not used:115 | |
| |> not used:116 | |
__________________________________________
Information: Macrocell Utilization.
Description Used Max
____________________________________
| I/O Macrocells | 13 | 16 |
| PIM Input Connects | 14 | 36 |
____________________________________
27 / 52 = 51 %
----------------------------------------------------------------------------
PLD Compiler Software: C37XFIT.EXE 19 JUN1998 [v4.02 ] 4 IR x96
DESIGN SIGNAL PLACEMENT (20:37:42)
Device: c371i
Package: CY7C371I-66AC
39 : GND
40 : Not Used
41 : Not Used
42 : s1
43 : Not Used
44 : Not Used
1 : Reserved1
2 : Not Used
3 : s3
4 : Not Used
5 : VPP
6 : GND
7 : clk
8 : Not Used
9 : Not Used
10 : Not Used
11 : Not Used
12 : Not Used
13 : Reserved2
14 : reset_n
15 : Not Used
16 : VCC
17 : GND
18 : s2
19 : adstart
20 : (licznik_9)
21 : (licznik_5)Reserved3
22 : (licznik_1)
23 : (licznik_0)
24 : clk_4
25 : (licznik_3)
26 : Not Used
27 : Not Used
28 : GND
29 : Not Used
30 : (licznik_6)
31 : (licznik_7)
32 : (licznik_10)
33 : (licznik_4)Reserved4
34 : (licznik_8)
35 : Not Used
36 : Not Used
37 : Not Used
38 : VCC
Information: Macrocell Utilization.
Description Used Max
____________________________________
| Dedicated Inputs | 0 | 3 |
| Clock/Inputs | 1 | 2 |
| I/O Macrocells | 18 | 32 |
____________________________________
19 / 37 = 51 %
Required Max (Available)
CLOCK/LATCH ENABLE signals 1 2
Input REG/LATCH signals 0 4
Input PIN signals 0 4
Input PINs using I/O cells 3 3
Output PIN signals 15 29
Total PIN signals 19 37
Macrocells Used 15 32
Unique Product Terms 25 160
----------------------------------------------------------------------------
PLD Compiler Software: C37XFIT.EXE 19 JUN1998 [v4.02 ] 4 IR x96
PRESET/RESET AND OUTPUT ENABLE COMBINATIONS
PRESET: GND
RESET : /reset_n
Used by Logic Blocks: AB
Total unique inputs = 14
count of registered equations = 15
==>OE: GND or VCC
count of OE equations = 15
----------------------------------------------------------------------------
PLD Compiler Software: C37XFIT.EXE 19 JUN1998 [v4.02 ] 4 IR x96
TIMING PATH ANALYSIS (20:37:42) using Package: CY7C371I-66AC
Messages:
----------------------------------------------------------------------------
Signal Name | Delay Type | tmax | Path Description
----------------------------------------------------------------------------
reg::s1[42]
inp::clk_4.Q
tSCS 15.0 ns 1 pass
inp::reset_n
tRO 24.0 ns 1 pass
out::s1
tCO 10.0 ns
----------------------------------------------------------------------------
reg::s3[3]
inp::clk_4.Q
tSCS 15.0 ns 1 pass
inp::reset_n
tRO 24.0 ns 1 pass
out::s3
tCO 10.0 ns
----------------------------------------------------------------------------
reg::s2[18]
inp::clk_4.Q
tSCS 15.0 ns 1 pass
inp::reset_n
tRO 24.0 ns 1 pass
out::s2
tCO 10.0 ns
----------------------------------------------------------------------------
reg::adstart[19]
inp::s1.Q
tSCS 15.0 ns 1 pass
inp::reset_n
tRO 24.0 ns 1 pass
out::adstart
tCO 10.0 ns
----------------------------------------------------------------------------
reg::(licznik_9)[20]
inp::clk_4.Q
tSCS 15.0 ns 1 pass
inp::reset_n
tRO 24.0 ns 1 pass
out::licznik_9
tCO 10.0 ns
----------------------------------------------------------------------------
reg::(licznik_5)Reserved3[21]
inp::clk_4.Q
tSCS 15.0 ns 1 pass
inp::reset_n
tRO 24.0 ns 1 pass
out::licznik_5
tCO 10.0 ns
----------------------------------------------------------------------------
reg::(licznik_1)[22]
inp::licznik_0.Q
tSCS 15.0 ns 1 pass
inp::reset_n
tRO 24.0 ns 1 pass
out::licznik_1
tCO 10.0 ns
----------------------------------------------------------------------------
reg::(licznik_0)[23]
inp::licznik_1.Q
tSCS 15.0 ns 1 pass
inp::reset_n
tRO 24.0 ns 1 pass
out::licznik_0
tCO 10.0 ns
----------------------------------------------------------------------------
reg::clk_4[24]
inp::licznik_1.Q
tSCS 15.0 ns 1 pass
inp::reset_n
tRO 24.0 ns 1 pass
out::clk_4
tCO 10.0 ns
----------------------------------------------------------------------------
reg::(licznik_3)[25]
inp::clk_4.Q
tSCS 15.0 ns 1 pass
inp::reset_n
tRO 24.0 ns 1 pass
out::licznik_3
tCO 10.0 ns
----------------------------------------------------------------------------
reg::(licznik_6)[30]
inp::clk_4.Q
tSCS 15.0 ns 1 pass
inp::reset_n
tRO 24.0 ns 1 pass
out::licznik_6
tCO 10.0 ns
----------------------------------------------------------------------------
reg::(licznik_7)[31]
inp::clk_4.Q
tSCS 15.0 ns 1 pass
inp::reset_n
tRO 24.0 ns 1 pass
out::licznik_7
tCO 10.0 ns
----------------------------------------------------------------------------
reg::(licznik_10)[32]
inp::clk_4.Q
tSCS 15.0 ns 1 pass
inp::reset_n
tRO 24.0 ns 1 pass
out::licznik_10
tCO 10.0 ns
----------------------------------------------------------------------------
reg::(licznik_4)Reserved4[33]
inp::clk_4.Q
tSCS 15.0 ns 1 pass
inp::reset_n
tRO 24.0 ns 1 pass
out::licznik_4
tCO 10.0 ns
----------------------------------------------------------------------------
reg::(licznik_8)[34]
inp::clk_4.Q
tSCS 15.0 ns 1 pass
inp::reset_n
tRO 24.0 ns 1 pass
out::licznik_8
tCO 10.0 ns
----------------------------------------------------------------------------
Worst Case Path Summary
-----------------------
tSCS = 15.0 ns for s1.D
tCO = 10.0 ns for s1.C
tRO = 24.0 ns for s1.AR
Summary:
Error Count = 0 Warning Count = 0
Completed Successfully
----------------------------------------------------------------------------
PLD Compiler Software: C37XFIT.EXE 19 JUN1998 [v4.02 ] 4 IR x96
JEDEC ASSEMBLE (20:37:42)
Messages:
Information: Processing JEDEC for Logic Block 1.
Information: Processing JEDEC for Logic Block 2.
Information: JEDEC output file 'gal0.jed' created.
Summary:
Error Count = 0 Warning Count = 0
Completed Successfully at 20:37:42