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Zabawe mozesz zaczac skladajac sobie w kilka chwil malego CPLD w obudowie
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-- [ Artur M. Piwko : Pipen : AMP29-RIPE : RLU:100918 : From == Trap! : SIG:224B ] [ 12:39:02 user up 10898 days, 0:34, 1 user, load average: 0.06, 0.06, 0.06 ] If at first you don't succeed, to heck with it. ======== Path: news-archive.icm.edu.pl!newsfeed.gazeta.pl!news.nask.pl!news.nask.org.pl!newsfeed.tpinternet.pl!nemesis.news.tpi.pl!atlantis.news.tpi.pl!news.tpi.pl!not-for-mail From: antispam_verox_at_nospam_bijspamera.veroxsystems.com (Verox) Newsgroups: pl.misc.elektronika Subject: Re: VHDL, verilog Linux Date: Sat, 25 Feb 2006 13:28:22 +0000 (UTC) Organization: tp.internet - http://www.tpi.pl/ Lines: 35 Message-ID: <slrne00moq.5kg.antispam_verox_at_nospam_matrix.veroxsystems.com> References: <slrndvv8dp.5kg.antispam_verox_at_nospam_matrix.veroxsystems.com> <469o23Fa6sinU1_at_nospam_uni-berlin.de> <slr